ICS85354AK ICST [Integrated Circuit Systems], ICS85354AK Datasheet - Page 9

• Manufacturer Part Number: ICS85354AK
• Description: DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
• Manufacturer: ICST [Integrated Circuit Systems]

W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
85354AK
RTT =
ERMINATION FOR
IRING THE
((V
F
FOUT
OH
IGURE
+ V
D
OL
Integrated
Circuit
Systems, Inc.
2A. LVPECL O
IFFERENTIAL
) / (V
1
CC
3.3V LVPECL O
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
F
IGURE
I
Z
NPUT TO
o
50Ω
UTPUT
Single Ended Clock Input
1. S
A
T
RTT
A
ERMINATION
INGLE
UTPUTS
50Ω
PPLICATION
www.icst.com/products/hiperclocks.html
CCEPT
PRELIMINARY
V
CC
E
FIN
- 2V
NDED
C1
0.1u
S
V_REF
INGLE
CC
S
/2 is
IGNAL
D
E
9
IFFERENTIAL
I
NDED
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
D
NFORMATION
1K
RIVING
R1
1K
R2
VCC
L
FOUT
EVELS
F
D
nCLKx
IGURE
CLKx
IFFERENTIAL
-
2B. LVPECL O
TO
-LVPECL/ECL M
Z
Z
o
o
I
= 50Ω
= 50Ω
NPUT
CC
125Ω
84Ω
= 3.3V, V_REF should be 1.25V
UTPUT
3.3V
125Ω
84Ω
ICS85354
T
D
ERMINATION
UAL
REV. B JUNE 8, 2004
ULTIPLEXER
FIN
2:1/1:2