CY7C1354C CYPRESS [Cypress Semiconductor], CY7C1354C Datasheet - Page 8

• Manufacturer Part Number: CY7C1354C
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05538 Rev. *G
Because the CY7C1354C and CY7C1356C are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH
(DQ
CY7C1356C) inputs. Doing so will tri-state the output drivers.
As a safety precaution, DQ
CY7C1354C and
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1354C/CY7C1356C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subse-
quent clock rise, the chip enables (CE
WE inputs are ignored and the burst counter is incremented.
The correct BW (BW
CY7C1356C) inputs must be driven in each cycle of the burst
write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
2. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =
3. Write is defined by WE and BW
4. When a write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.
6. CEN = H inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
is inactive or when the device is deselected, and DQs = data when OE is active.
a,b,c,d
Parameter
before
/DQP
[2, 3, 4, 5, 6, 7, 8]
a,b,c,d
Operation
presenting
DQ
for CY7C1354C and DQ
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
a,b,c,d
a,b
/DQP
X
and DQP
for CY7C1354C and BW
. See Write Cycle Description table for details.
data
a,b
Description
to
(DQ
for CY7C1356C) are
1
, CE
the
a,b,c,d
Address
External
External
External
2
, and CE
Used
None
None
Next
Next
Next
/DQP
DQ
a,b
/DQP
and
a,b,c,d
3
a,b
a,b
CE ZZ
) and
H
X
X
X
X
L
L
L
DQP
for
for
for
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
L
L
L
L
L
L
L
L
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
the duration of t
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
DD
ADV/LD
DD
Address
Address
− 0.2V
H
H
Test Conditions
− 0.2V
H
H
L
L
L
L
A1,A0
A1,A0
First
First
00
01
10
00
01
10
11
11
WE BWx
H
H
X
X
X
X
X
L
ZZREC
Address
Address
Second
X
X
X
X
X
X
L
L
Second
A1,A0
A1,A0
1
01
10
11
00
, CE
01
00
10
11
after the ZZ input returns LOW.
OE
2
H
H
X
X
X
L
L
X
, and CE
DD
CEN CLK
)
2t
L
L
L
L
L
L
L
L
Address
Address
Min.
A1,A0
CYC
A1,A0
Third
3,
0
Third
10
00
01
11
10
00
01
11
must remain inactive for
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
CY7C1354C
CY7C1356C
X
2t
2t
Max.
= Tri-state when OE
50
CYC
CYC
Data Out (Q)
Data Out (Q)
Data In (D)
Data In (D)
Page 8 of 28
Tri-State
Tri-State
Tri-State
Tri-State
Address
Address
Fourth
Fourth
A1,A0
A1,A0
DQ
10
01
00
11
00
01
10
11
Unit
mA
ns
ns
ns
ns
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