CY7C1356C CYPRESS [Cypress Semiconductor], CY7C1356C Datasheet
CY7C1356C
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CY7C1356C Summary of contents
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... SRAMs with No Bus Latency™ (NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354C and CY7C1356C are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle ...
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... Logic Block Diagram – CY7C1356C (512 K × 18) A0, A1, A MODE CLK C CEN WRITE ADDRESS ADV/ CE1 CE2 CE3 ZZ Document Number: 38-05538 Rev. *K ADDRESS REGISTER BURST A0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 1 REGISTER 2 WRITE REGISTRY AND DATA COHERENCY ...
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... TAP AC Switching Characteristics ............................... 14 3.3 V TAP AC Test Conditions ....................................... 15 3.3 V TAP AC Output Load Equivalent ......................... 15 2.5 V TAP AC Test Conditions ....................................... 15 2.5 V TAP AC Output Load Equivalent ......................... 15 Document Number: 38-05538 Rev. *K CY7C1354C, CY7C1356C TAP DC Electrical Characteristics and Operating Conditions ............................................. 15 Identification Register Definitions ................................ 15 Scan Register Sizes ....................................................... 16 Identification Codes ....................................................... 16 Boundary Scan Exit Order (256 K × ...
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... DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1354C, CY7C1356C 166 MHz Unit 3.5 ns 180 DDQ DQPa 74 DQa 73 DQa DDQ ...
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... CEN DQP MODE NC/72M TMS TDI TCK TDO CY7C1356C (512 NC/18M ADV/ ...
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... TDI A1 TDO TCK TMS CY7C1356C (512 K × 18 CEN CLK ...
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... CE to select/deselect the device select/deselect the device. 2 –DQ are placed in a tristate condition. The outputs are controlled DQP controlled CY7C1354C, CY7C1356C and DQP , BW controls DQ and DQP During [a:d]. is controlled DQP is controlled ...
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... On the next clock rise the data presented to DQ (DQ /DQP a,b,c,d CY7C1356C or a subset for byte write operations, see the table Partial Write Cycle Description on page 10 latched into the device and the write is complete. CY7C1354C, CY7C1356C Single Read – ...
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... The output enable (OE) can be deasserted HIGH before presenting data to (DQ /DQP for CY7C1354C and DQ a,b,c,d a,b,c,d CY7C1356C) inputs. Doing so will tristate the output drivers safety precaution, DQ (DQ and DQP CY7C1354C and DQ /DQP for a,b a,b automatically tristated during the data portion of a write cycle, regardless of the state of OE ...
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... Truth Table The Truth Table for CY7C1354C and CY7C1356C follows. Operation Deselect cycle Continue deselect cycle Read cycle (begin burst) Read cycle (continue burst) NOP/dummy read (begin burst) Dummy read (continue burst) Write cycle (begin burst) Write cycle (continue burst) NOP/WRITE ABORT (begin burst) ...
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... Partial Write Cycle Description The following table lists the Partial Write Cycle Description for CY7C1356C. Function (CY7C1356C) Read Write – no bytes written Write byte a (DQ and DQP a a) Write byte b – (DQ and DQP b b) Write both bytes Notes 10 “Don't Care” Logic HIGH Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one bytewrite select is active, BWx = valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1354C/CY7C1356C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149 ...
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... Capture-DR state, an input or output undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. CY7C1354C, CY7C1356C INTEST or the PRELOAD ...
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... These instructions are not implemented but are reserved for future use. Do not use these instructions TDIS t TDIH t TDOV t TDOX DON’ UNDEFINED Description / ns CY7C1354C, CY7C1356C 5 6 Min Max Unit 50 – ns – 20 MHz 20 – – ns – – ...
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... DDQ V = 3.3 V DDQ V = 2.5 V DDQ V = 3.3 V DDQ V = 2.5 V DDQ GND < V < DDQ CY7C1354C CY7C1356C 000 000 01011001000010110 Reserved for future use. 00000110100 00000110100 1 1 CY7C1354C, CY7C1356C to 2 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 – V 2.0 – V 2.9 – V 2.1 – V – 0.4 V – ...
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... RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 38-05538 Rev. *K CY7C1354C, CY7C1356C Bit Size (× 36) Bit Size (× 18 ...
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... Not Bonded Not Bonded (Preset to 1) (Preset CY7C1354C, CY7C1356C Page ...
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... R11 64 B2 R10 65 Not Bonded (Preset to 0) Not Bonded (Preset to 0) P10 Not Bonded (Preset CY7C1354C, CY7C1356C 165-ball Not Bonded (Preset ...
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... DD V output disabled I DDQ, /2), undershoot: V (AC) > –2 V (Pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1354C, CY7C1356C Description Test Condi- Typ Max* Unit tions Logical 25 °C 320 368 single-bit upsets Logical 25 °C 0 0.01 multi-bit upsets Single event 85 ° ...
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... 3 2 DDQ 5 5 100 TQFP Test Conditions Max Test conditions follow standard 29.41 test methods and procedures for measuring thermal 6.13 impedance, per EIA/JESD51. CY7C1354C, CY7C1356C Min Max Unit – 250 mA – 220 mA – 180 mA – 130 mA – 120 mA – ...
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... R = 351 INCLUDING JIG AND SCOPE ( 1667 2 DDQ GND 1538 INCLUDING JIG AND (b) SCOPE CY7C1354C, CY7C1356C ALL INPUT PULSES 90% 90% 10% 10% (c) ALL INPUT PULSES 90% 90% 10% 10% (c) Page ...
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... V minimum initially, before a Read or Write operation can be DD and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1354C, CY7C1356C –200 –166 Unit Min Max Min Max 1 – ...
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... DOH CLZ D(A1) D(A2) D(A2+1) Q(A3) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1354C, CY7C1356C OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH. ...
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... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. Document Number: 38-05538 Rev. *K [31, 32, 33 D(A1) Q(A2) Q(A3) READ WRITE STALL NOP Q(A3) D(A4) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH LOW CY7C1354C, CY7C1356C CHZ D(A4) Q(A5) READ DESELECT CONTINUE Q(A5) DESELECT is HIGH. 3 Page [+] Feedback ...
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... Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 35. I/Os are in high Z when exiting ZZ sleep mode. Document Number: 38-05538 Rev. *K [34, 35] Figure 7. ZZ Mode Timing DDZZ High-Z DON’T CARE CY7C1354C, CY7C1356C t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback ...
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... Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free CY7C1356C-250AXC Ordering Code Definitions CY 7C 135X C - XXX XX X Document Number: 38-05538 Rev. *K CY7C1354C, CY7C1356C www.cypress.com and refer to the product summary page at Part and Package Type Temperature Range Commercial I = Industrial Package Type ...
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... Package Diagrams Figure 8. 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm), 51-85050 Document Number: 38-05538 Rev. *K CY7C1354C, CY7C1356C 51-85050 *D Page [+] Feedback ...
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... Figure 9. 119-ball BGA (14 × 22 × 2.4 mm), 51-85115 Document Number: 38-05538 Rev. *K CY7C1354C, CY7C1356C 51-85115 *C Page [+] Feedback ...
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... Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm), 51-85180 Document Number: 38-05538 Rev. *K CY7C1354C, CY7C1356C 51-85180 *C Page [+] Feedback ...
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... TDI test data input TMS test mode select TDO test data output TQFP thin quad flat pack WE write enable Document Number: 38-05538 Rev. *K CY7C1354C, CY7C1356C Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes ...
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... Document History Page Document Title: CY7C1354C/CY7C1356C 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05538 Submission REV. ECN No. Date ** 242032 See ECN *A 278130 See ECN *B 284431 See ECN *C 320834 See ECN *D 351895 See ECN *E 377095 See ECN ...
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... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05538 Rev Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised March 2, 2011 CY7C1354C, CY7C1356C PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...