CY7C1361A CYPRESS [Cypress Semiconductor], CY7C1361A Datasheet - Page 13

• Manufacturer Part Number: CY7C1361A
• Description: 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05259 Rev. *A
TAP AC Switching Characteristics
TAP Timing and Test Conditions
Notes:
TEST MODE SELECT
16. t
17. Test conditions are specified using the load in TAP AC test conditions.
t
fTF
t
t
Output Times
tTLQX
tTLQV
tDVTH
tTHDX
Set-up Times
tMVTH
t
tCS
tTHMX
t
tCH
THTH
THTL
TLTH
TDIS
TDIH
Clock
Hold Times
Parameter
CS
TDO
TEST DATA OUT
and t
TEST DATA IN
TEST CLOCK
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
Z
0
(TMS)
(TDO)
(TCK)
= 50
(TDI)
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
TCK LOW to TDO Unknown
TCK LOW to TDO Valid
TDI Valid to TCK HIGH
TCK HIGH to TDI Invalid
TMS Set-up
TDI Set-up to TCK Clock Rise
Capture Set-up
TMS Hold
TDI Hold after Clock Rise
Capture Hold
(a)
Vt = 1.5V
50
t
THTH
20 pF
t
t
MVTH
DVTH
Over the Operating Range
Description
t
t
THMX
THDX
t
V
TLQX
t
THTL
SS
t
TLQV
[16, 17]
1.5 ns
3.0V
ALL INPUT PULSES
1.5V
(b)
t
TLTH
Min.
20
8
8
0
5
5
5
5
5
5
5
5
1.5 ns
CY7C1361A
CY7C1363A
Max.
50
10
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MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns