CY7C1412AV18-250BZXI CYPRESS [Cypress Semiconductor], CY7C1412AV18-250BZXI Datasheet - Page 18

• Manufacturer Part Number: CY7C1412AV18-250BZXI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05615 Rev. *D
Power Up Sequence in QDR-II SRAM
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
Power Up Waveforms
Notes:
13. It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
14. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
• Apply power and drive DOFF LOW (All other inputs can be
• After the power and clock (K, K, C, C) are stable take DOFF
• The additional 1024 cycles of clocks are required for the
V
HIGH or LOW)
— Apply V
— Apply V
HIGH
DLL to lock.
DD
/
DOFF
V
DDQ
K
K
DD
DDQ
before V
before V
DDQ
REF
Unstable Clock
Clock Start (Clock Starts after
or at the same time as V
V
DD
[13, 14]
/
V
DDQ
REF
Stable (< +/- 0.1V DC per 50ns )
V
DD
/
V
DLL Constraints
DDQ
• DLL uses either K or C clock as its synchronizing input.The
• The DLL functions at frequencies down to 80MHz.
• If the input clock is unstable and the DLL is enabled, then
Fix High (or tied to V DDQ )
input must have low phase jitter, which is specified as t
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior
> 1024 Stable clock
Stable)
.
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
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Operation
Page 18 of 25
KC Var
.