CY7C144AV CYPRESS [Cypress Semiconductor], CY7C144AV Datasheet - Page 13

• Manufacturer Part Number: CY7C144AV
• Description: 3.3V 8K/16K x 8 Dual-Port Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Document #: 38-06051 Rev. *E
Notes
32. CE = HIGH for the duration of the above timing (both write and read cycle).
33. I/O
34. Semaphores are reset (available to both ports) at cycle start.
35. If t
A
A
A
0R
SPS
0L
0R
0
SEM
SEM
–A
SEM
R/W
R/W
I/O
R/W
–A
–A
OE
= I/O
is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
2
2L
0
2R
R
L
R
L
0L
= LOW (request semaphore); CE
t
SA
Figure 7. Timing Diagram of Semaphore Contention
Figure 6. Semaphore Read After Write Timing, Either Side
(continued)
VALID ADRESS
t
AW
WRITE CYCLE
t
t
R
PWE
SCE
= CE
t
SD
DATA
t
MATCH
SPS
MATCH
L
= HIGH.
t
IN
HA
VALID
t
HD
t
SWRD
t
SOP
t
SOP
READ CYCLE
t
SAA
VALID ADRESS
t
DOE
t
ACE
[33, 34, 35]
[32]
DATA
OUT
VALID
t
OHA
CY7C144AV
CY7C006AV
Page 13 of 21
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