CAT24WC32 CATALYST [Catalyst Semiconductor], CAT24WC32 Datasheet - Page 4

• Manufacturer Part Number: CAT24WC32
• Description: 32K/64K-Bit I2C Serial CMOS E2PROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

Doc. No. 1039, Rev. F
The CAT24WC32/64 supports the I
mission protocol. This Inter-Integrated Circuit Bus proto-
col defines any device that sends data to the bus to be
a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC32/64
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
The serial clock input clocks all data transferred into or
out of the device.
SCL
SDA
SDA OUT
Serial Clock
SDA IN
SCL
t SU:STA
SDA
SCL
8TH BIT
BYTE n
t F
START BIT
2
t HD:STA
C Bus data trans-
t LOW
ACK
t AA
t HD:DAT
t HIGH
STOP
CONDITION
4
t LOW
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
These pins are hardwired or left unconnected (for hard-
ware compatibility with CAT24WC16). When hardwired,
up to eight CAT24WC32/64s may be addressed on a
single bus system (refer to Device Addressing ). When
the pins are left unconnected, the default values are
zeros.
This input, when tied to GND, allows write operations to
the entire memory. For CAT24WC32/64 when this pin
is tied to Vcc, the entire memory is write protected.
When left floating, memory is unprotected.
t DH
Write Protect
t WR
Serial Data/Address
t SU:DAT
t R
Device Address Inputs
STOP BIT
START
CONDITION
t SU:STO
t BUF
ADDRESS
5020 FHD F03
5020 FHD F04
5020 FHD F05