CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet
CY7C1470BV33_11
Related parts for CY7C1470BV33_11
CY7C1470BV33_11 Summary of contents
Page 1
M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Pin-compatible and functionally equivalent to ZBT™ ■ Supports 250 MHz bus operations with zero wait states ■ Available speed grades are 250, 200, ...
Page 2
Logic Block Diagram – CY7C1470BV33 (2 M × 36) A0, A1, A MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ CE1 CE2 CE3 ZZ Logic Block Diagram – CY7C1472BV33 ...
Page 3
Logic Block Diagram – CY7C1474BV33 (1 M × 72) A0, A1, A MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ CE1 ...
Page 4
Contents Pin Configurations ........................................................... 5 Pin Definitions .................................................................. 8 Functional Overview ...................................................... 10 Single Read Accesses .............................................. 10 Burst Read Accesses ................................................ 10 Single Write Accesses ............................................... 10 Burst Write Accesses ................................................ 10 Sleep Mode ............................................................... 11 Interleaved Burst Address ...
Page 5
Pin Configurations DQPc 1 DQc 2 DQc DDQ DQc 6 DQc 7 DQc 8 DQc DDQ 11 DQc 12 DQc CY7C1470BV33 ...
Page 6
Pin Configurations (continued NC/576M NC/1G A CE2 C DQP DDQ DDQ DDQ ...
Page 7
Pin Configurations (continued DQg DQg A B DQg DQg BWS C DQg DQg BWS D DQg DQg DQPg DQPc V DDQ F DQc DQc DQc DQc V DDQ H DQc ...
Page 8
Pin Definitions Pin Name IO Type A0 Input- Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge A1 Synchronous of the CLK Input- Byte Write Select Inputs, Active LOW. Qualified with WE ...
Page 9
Pin Definitions (continued) Pin Name IO Type TDI JTAG Serial Input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. Synchronous TMS Test Mode Select This pin Controls the Test Access Port State Machine. Sampled ...
Page 10
Functional Overview The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during read or write transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock ...
Page 11
When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables ( and are ignored and the burst counter is incremented. The ...
Page 12
Truth Table The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. Operation Address Used Deselect Cycle None Continue Deselect None Cycle Read Cycle External (Begin Burst) Read Cycle Next (Continue Burst) NOP/Dummy Read External (Begin Burst) Dummy Read Next (Continue ...
Page 13
Partial Write Cycle Description The partial write cycle description for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. Function (CY7C1470BV33) Read Write – No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – (DQ and DQP ...
Page 14
IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full ...
Page 15
Instruction Register Three bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 14. During power ...
Page 16
CLK captured in the boundary scan register. After the data is captured possible to shift out the data by putting the TAP into the Shift-DR ...
Page 17
TAP AC Switching Characteristics [12, 13] Over the Operating Range Parameter Clock t TCK Clock Cycle Time TCYC t TCK Clock Frequency TF t TCK Clock HIGH time TH t TCK Clock LOW time TL Output Times t TCK Clock ...
Page 18
V TAP AC Test Conditions Input pulse levels................................................V Input rise and fall times....................................................1 ns Input timing reference levels.......................................... 1.5 V Output reference levels ................................................. 1.5 V Test load termination supply voltage ............................. 1.5 V 3.3 V TAP AC Output ...
Page 19
Identification Register Definitions CY7C1470BV33 Instruction Field (2 M × 36) Revision Number (31:29) 000 [15] Device Depth (28:24) 01011 Architecture/Memory 001000 Type(23:18) Bus Width/Density(17:12) 100100 Cypress JEDEC ID Code 00000110100 (11:1) ID Register Presence 1 Indicator (0) Scan Register Sizes ...
Page 20
Boundary Scan Exit Order (2 M × 36) Bit # 165-ball ID Bit # ...
Page 21
Boundary Scan Exit Order (1 M × 72) Bit # 209-ball ID Bit # ...
Page 22
Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage on V Relative to ...
Page 23
Electrical Characteristics (continued) [16, 17] Over the Operating Range Parameter Description [18 Operating Supply Automatic CE SB1 Power Down Current—TTL Inputs I Automatic CE SB2 Power Down Current—CMOS Inputs I Automatic CE SB3 Power Down ...
Page 24
Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description C Address Input Capacitance ADDRESS C Data Input Capacitance DATA C Control Input Capacitance CTRL C Clock Input Capacitance CLK C Input/Output Capacitance ...
Page 25
Switching Characteristics [19, 20] Over the Operating Range Parameter Description [21 (typical) to the First Access Read or Write Power CC Clock t Clock Cycle Time CYC F Maximum Operating Frequency MAX t Clock HIGH CH t Clock ...
Page 26
Switching Waveforms Figure 3 shows read-write timing waveform CYC CLK CENS CENH CL CH CEN t t CES CEH CE ADV/ ADDRESS ...
Page 27
Switching Waveforms (continued) Figure 4 shows NOP, STALL and DESELECT Cycles waveform. Figure 4. NOP, STALL and DESELECT Cycles CLK CEN CE ADV/LD WE BWx A1 A2 ADDRESS Data In-Out (DQ) WRITE READ STALL D(A1) Q(A2) Figure ...
Page 28
Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at http://www.cypress.com/products. Cypress maintains a ...
Page 29
Package Diagrams Document #: 001-15031 Rev. *H CY7C1472BV33, CY7C1474BV33 Figure 6. 100-pin TQFP (14 × 20 × 1.4 mm) Figure 7. 165-ball FBGA (15 × 17 × 1.4 mm) CY7C1470BV33 51-85050 *D 51-85165 *B Page [+] Feedback ...
Page 30
Package Diagrams (continued) Document #: 001-15031 Rev. *H CY7C1472BV33, CY7C1474BV33 Figure 8. 209-ball FBGA (14 × 22 × 1.76 mm) CY7C1470BV33 51-85167 *A Page [+] Feedback ...
Page 31
Acronyms Acronym Description CMOS complementary metal oxide semiconductor FBGA fine-pitch ball grid array I/O input/output JTAG Joint Test Action Group LSB least significant bit LMBU Logical Multi Bit Upsets LSBU Logical Single Bit Upsets MSB most significant bit OE output ...
Page 32
Document History Page Document Title: CY7C1470BV33/CY7C1472BV33/CY7C1474BV33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Document Number: 001-15031 Orig. of Revision ECN Change ** 1032642 VKN/KKVTMP *A 1897447 VKN/AESA *B 2082487 VKN *C ...
Page 33
Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive cypress.com/go/automotive Clocks & ...