CY7C1471BV25_11 CYPRESS [Cypress Semiconductor], CY7C1471BV25_11 Datasheet
CY7C1471BV25_11
Related parts for CY7C1471BV25_11
CY7C1471BV25_11 Summary of contents
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Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-Through SRAM with NoBL™ Architecture Features No Bus Latency™ (NoBL™) architecture eliminates dead ■ cycles between write and read cycles Supports up to 133 ...
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Logic Block Diagram – CY7C1471BV25 (2 M × 36) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN ADV/ READ LOGIC CE1 CE2 CE3 ZZ Logic Block Diagram – ...
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Logic Block Diagram – CY7C1475BV25 (1 M × 72) ADDRESS A0, A1, A REGISTER 0 MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ ...
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Contents Pin Configurations ........................................................... 5 Pin Definitions .................................................................. 9 Functional Overview ...................................................... 10 Single Read Accesses .............................................. 10 Burst Read Accesses ................................................ 10 Single Write Accesses ............................................... 10 Burst Write Accesses ................................................ 11 Sleep Mode ............................................................... 11 Interleaved Burst Address ...
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Pin Configurations DQP DDQ BYTE DDQ ...
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Pin Configurations (continued DDQ DDQ ...
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Pin Configurations (continued) 165-ball FBGA (15 × 17 × 1.4 mm) Pinout NC/576M NC/1G A CE2 C DQP DDQ DDQ ...
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Pin Configurations (continued) 209-ball FBGA (14 × 22 × 1.76 mm) Pinout DQg DQg B DQg DQg BWS C DQg DQg BWS D DQg DQg E DQPg DQPc F DQc DQc G DQc DQc H DQc DQc ...
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Pin Definitions Name Input- Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge 0 1 Synchronous of the CLK Input- Byte Write Inputs, ...
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Pin Definitions (continued) Name IO TDI JTAG serial input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not used, leave this pin floating or connected to V available ...
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Byte Write capability is included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. Because the CY7C1471BV25, CY7C1473BV25, CY7C1475BV25 are common IO devices, data must not be driven into ...
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Truth Table The truth table for CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 follows. Address Operation Used Deselect Cycle None Deselect Cycle None Deselect Cycle None Continue Deselect Cycle None Read Cycle (Begin Burst) External Read Cycle (Continue Burst) Next NOP/Dummy Read External ...
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Truth Table for Read/Write The read-write truth table for CY7C1471BV25 follows. Function Read Write No bytes written Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Byte C ...
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IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 incorporate a serial boundary scan Test Access Port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full ...
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TAP Registers Registers are connected between the TDI and TDO balls and enable the scanning of data into and out of the SRAM test circuitry. Only one register is selectable at a time through the instruction register. Data is serially ...
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Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct signal value, make certain that the SRAM signal is stabilized long enough to meet the ...
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TAP AC Switching Characteristics [11, 12] Over the Operating Range Parameter Clock t TCK Clock Cycle Time TCYC t TCK Clock Frequency TF t TCK Clock HIGH Time TH t TCK Clock LOW Time TL Output Times t TCK Clock ...
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Identification Register Definitions CY7C1471BV25 Instruction Field (2 M × 36) Revision Number (31:29) Device Depth (28:24) Architecture/Memory Type (23:18) Bus Width/Density (17:12) Cypress JEDEC ID Code (11:1) 00000110100 ID Register Presence Indicator (0) Scan Register Sizes Register Name Instruction Bypass ...
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Boundary Scan Exit Order (2 M × 36) Bit # 165-ball ID Bit # ...
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Boundary Scan Exit Order (1 M × 72) Bit # 209-ball ID Bit # ...
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Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied .......................................... –55C to +125 C Supply Voltage on ...
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Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description C Address Input Capacitance ADDRESS C Data Input Capacitance DATA C Control Input Capacitance CTRL C Clock Input Capacitance CLK C Input-Output Capacitance ...
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Switching Characteristics [17, 18] Over the Operating Range Parameter [19] t POWER Clock t Clock Cycle Time CYC t Clock HIGH CH t Clock LOW C]L Output Times t Data Output Valid After CLK Rise CDV t Data Output Hold ...
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Switching Waveforms Figure 5 shows read-write timing waveform CYC CLK t CENS t CENH t CH CEN t CES t CEH CE ADV/ ADDRESS D(A1) t ...
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Switching Waveforms (continued) Figure 6 shows NOP, STALL and DESELECT Cycles waveform CLK CEN CE ADV/ [A: ADDRESS D(A1) DQ COMMAND WRITE READ D(A1) Q(A2) Notes 26. For this waveform ZZ is tied LOW. ...
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Switching Waveforms (continued) Figure 7 shows ZZ Mode timing waveform. CLK ZZI I SUPPLY I ALL INPUTS (except ZZ) Outputs (Q) Notes 29. Device must be deselected when entering ZZ mode. See 30. DQs are in high ...
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Ordering Information Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website ...
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Package Diagrams Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050 Document Number: 001-15013 Rev. *H CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 51-85050 *D Page [+] Feedback ...
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Package Diagrams (continued) Figure 9. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85165 Document Number: 001-15013 Rev. *H CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 51-85165 *B Page [+] Feedback ...
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Package Diagrams (continued) Figure 10. 209-ball FBGA (14 × 22 × 1.76 mm), 51-85167 Document Number: 001-15013 Rev. *H CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 51-85167 *A Page [+] Feedback ...
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Acronyms Acronym Description BWS byte write select BGA ball grid array CMOS complementary metal oxide semiconductor FBGA fine-pitch ball grid array I/O input/output JTAG Joint Test Action Group LSB least significant bit MSB most significant bit OE output enable SRAM ...
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Document History Page Document Title: CY7C1471BV25/CY7C1473BV25/CY7C1475BV25, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 001-15013 Orig. of REV. ECN NO. Issue Date Change ** 1024500 See ECN VKN/KKVTMP New Data ...
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