AD9520-5 AD [Analog Devices], AD9520-5 Datasheet

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... The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-5 is used, it refers to that specific member of the AD9520 family. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use ...

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... AD9520-5 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 7 Clock Outputs ............................................................................... 7 Timing Characteristics ................................................................ 8 Timing Diagrams ..................................................................... 9 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ......................... 10 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ...

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... Pseudo-End-of-Data (Operational Code 0xFE) ................. 54 Thermal Performance ..................................................................... 55 Register Map .................................................................................... 56 Register Map Descriptions ............................................................. 61 Applications Information ............................................................... 75 Frequency Planning Using the AD9520 .................................. 75 Using the AD9520 Outputs for ADC Clock Applications .... 75 LVPECL Clock Distribution ...................................................... 75 CMOS Clock Distribution ......................................................... 76 Outline Dimensions ........................................................................ 77 Ordering Guide ........................................................................... 77 Rev Page AD9520-5 ...

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... AD9520-5 SPECIFICATIONS Typical (typ) is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5. noted. Minimum (min) and maximum (max) values are given over full VS and T POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ VS 3.135 3.3 VS_DRV 2.375 VCP VS RSET Pin Resistor 4.12 CPRSET Pin Resistor 5 ...

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... REF refers to REFIN (REF1)/REFIN (REF2) 560 1060 1310 ps When N delay and R delay are bypassed −320 +50 +240 ps When N delay = Setting 110 and R delay is bypassed Rev Page AD9520-5 is possible possible < VCP − 0 the voltage on the CP (charge CP CP < VCP − 0.5 V ...

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... AD9520-5 Parameter NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) @ 500 kHz PFD Frequency @ 1 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency PLL Figure of Merit (FOM) 2 PLL DIGITAL LOCK DETECT WINDOW Lock Threshold (Coincidence of Edges) Low Range (ABP 1 ...

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... VS_DRV − 0.84 VS_DRV − 1.79 VS_DRV − 1.64 820 950 250 0.1 0.5 0.6 Rev Page AD9520-5 Unit Test Conditions/Comments Termination = 50 Ω to VS_DRV − Differential (OUT, OUT) MHz Using direct to output; see Figure 17 (higher frequencies are possible, but amplitude will not meet the V OD specification) ...

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... AD9520-5 TIMING CHARACTERISTICS Table 5. Parameter LVPECL OUTPUT RISE/FALL TIMES Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVPECL OUTPUT PECL For All Divide Values Variation with Temperature 1 OUTPUT SKEW, LVPECL OUTPUTS LVPECL Outputs That Share the Same Divider ...

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... Timing Diagrams t CLK CLK t PECL t CMOS Figure 2. CLK/ CLK to Clock Output Timing, DIV = 1 DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential t FP Rev Page SINGLE-ENDED 80% CMOS 10pF LOAD 20 Figure 4. CMOS Timing, Single-Ended Load AD9520-5 ...

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... AD9520-5 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter CLK-TO-LVPECL ADDITIVE PHASE NOISE CLK = 1 GHz, Output = 1 GHz Divider = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 100 MHz Offset ...

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... Integration bandwidth = 12 kHz to 20 MHz 223 fs rms Calculated from SNR of ADC method Broadband jitter 209 fs rms Calculated from SNR of ADC method Broadband jitter Distribution section only; does not include the PLL 325 fs rms Calculated from SNR of ADC method Broadband jitter Rev Page AD9520-5 ...

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... AD9520-5 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 9. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz; Channel Divider = 2; Duty-Cycle Correction = Off CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = On CMOS OUTPUT ADDITIVE TIME JITTER CLK = 200 MHz ...

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... SET; STR 0.6 HLD; STR 0.6 1 120 140 C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL Rev Page AD9520-5 Max Unit Test Conditions/Comments V 0.3 × +10 μ 0.4 V 250 ...

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... AD9520-5 PD, SYNC, AND RESET PINS Table 12. Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming SYNC TIMING Pulse Width Low SERIAL PORT SETUP PINS: SP1, SP0 Table 13. ...

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... Additional CMOS outputs within the same channel turned Delta between divider bypassed (divide-by-1) and divide-by-2 to divide-by- Rev Page AD9520-5 − all CMOS CC = 200 MHz; VCO divider = 2; one LVPECL OUT = 200 MHz; VCO divider bypassed; one OUT = 62.5 MHz and capacitive loading ...

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... AD9520-5 ABSOLUTE MAXIMUM RATINGS Table 16. With Parameter or Pin Respect to VS GND VCP, CP GND VS_DRV GND REFIN, REFIN GND RSET GND CPRSET GND CLK, CLK GND CLK CLK SCLK/SCL, SDIO/SDA, SDO, CS GND OUT0, OUT0, OUT1, OUT1, GND OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, ...

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... Along with CLK, this pin is the differential input for the clock distribution section. Along with CLK, this pin is the differential input for the clock distribution section single-ended input is connected to the CLK pin, connect a 0.1 μF bypass capacitor from CLK to ground. Rev Page AD9520-5 48 OUT3 (OUT3A) 47 OUT3 (OUT3B) ...

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... AD9520-5 Input/ Pin Pin No. Output Type Mnemonic 15 I 3.3 V CMOS 3.3 V CMOS SCLK/SCL 17 I/O 3.3 V CMOS SDIO/SDA 18 O 3.3 V CMOS SDO 19 GND GND 20 I Three-level SP1 logic 21 I SP0 Three-level logic 22 I 3.3 V CMOS EEPROM 23 I 3.3 V CMOS RESET 24 I 3.3 V CMOS LVPECL or OUT9 (OUT9A) ...

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... PLL is not used. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1.This pin can be left unconnected when the PLL is not used. The exposed die pad must be connected to GND. Rev Page AD9520-5 ...

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... AD9520-5 TYPICAL PERFORMANCE CHARACTERISTICS 350 3 CHANNELS—6 LVPECL 300 3 CHANNELS—3 LVPECL 250 200 2 CHANNELS—2 LVPECL 150 1 CHANNEL—1 LVPECL 100 0 500 1000 1500 FREQUENCY (MHz) Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off), LVPECL Outputs Terminated 50 Ω to VS_DRV − 240 3 CHANNELS— ...

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... Figure 15. CMOS Output with 10 pF Load @ 25 MHz 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0 Figure 16. CMOS Output with 2 pF and 10 pF Load @ 250 MHz 2.0 1.8 1.6 1.4 1.2 1 Figure 17. LVPECL Differential Voltage Swing vs. Frequency Rev Page AD9520 TIME (ns) 2pF LOAD 10pF LOAD TIME (ns) 0.5 1.0 1 ...

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... AD9520-5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 100 200 300 400 FREQUENCY (MHz) Figure 18. CMOS Output Swing vs. Frequency and Capacitive Load –100 –110 –120 –130 –140 –150 –160 10 100 1k 10k 100k FREQUENCY (Hz) Figure 19. Additive (Residual) Phase Noise, CLK-to-LVPECL @ 245.76 MHz, Divide-by-1 –100 –110 2pF –120 – ...

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... Figure 23. Additive (Residual) Phase Noise, CLK-to-CMOS @ 250 MHz, Divide-by-4 –120 –130 –140 –150 –160 10M 100M 1k Figure 24. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) @ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz 10M 100M Rev Page AD9520-5 10k 100k 1M 10M 100M FREQUENCY (Hz) ...

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... AD9520-5 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter ...

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... N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE Figure 25. Rev Page AD9520-5 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV OUT0 OUT0 ...

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... AD9520-5 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9520 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 44 to Table 55). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. When the desired ...

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... DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE Figure 26. Clock Distribution or External VCO < 1600 MHz (Mode 1) Rev Page AD9520-5 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV ...

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... AD9520-5 Mode 2: High Frequency Clock Distribution—CLK or External VCO > 1600 MHz The AD9520 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide-by-6) ...

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... COUNTERS N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE Rev Page AD9520-5 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV OUT0 OUT0 ...

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... AD9520-5 Phase-Locked Loop (PLL) REF_SEL REFERENCE SWITCHOVER REF1 STATUS REF2 OPTIONAL REFIN STATUS BUF REFIN AMP CLK CLK The AD9520 includes on-chip PLL blocks that can be used with an external VCO or VCXO to create a complete phase-locked loop. The PLL requires an external loop filter, which usually consists of a small number of capacitors and resistors ...

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... Rev Page 85kΩ REF1 10kΩ 12kΩ 150Ω 150Ω 10kΩ 10kΩ VS REF2 85kΩ Figure 30. REFIN Equivalent Circuit for Non-XTAL Mode AD9520-5 Figure 30 VS ...

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... AD9520-5 There are several configurable modes of reference switchover. The switchover can be performed manually or automatically. Manual switchover is performed either through Register 0x01C or by using the REF_SEL pin. The automatic switchover occurs when REF1 disappears. There is also a switchover deglitch feature which ensures that the PLL does not receive rising edges that are far out of alignment with the newly selected reference ...

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... DM 12 120 DM 13 130 DM Rev Page AD9520-5 Notes (bypassed (bypassed and and and and and and ...

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... AD9520-5 Analog Lock Detect (ALD) The AD9520 provides an ALD function that can be selected for use at the LD pin. There are two operating modes for ALD: • N-channel open-drain lock detect. This signal requires a pull-up resistor to the positive supply, VS. The output is normally high with short, low going pulses. Lock is indicated by the minimum duty cycle of the low going pulses. • ...

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... PLL losing the reference clock; therefore, the holdover function puts the charge pump into a high impedance state to maintain the VCO frequency as close as possible to the original frequency before the reference clock disappeared. A flowchart of the automatic/internal holdover function operation is shown in Figure 34. Rev Page AD9520-5 ...

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... AD9520-5 PLL ENABLED DLD == LOW YES WAS LD PIN == HIGH WHEN DLD WENT LOW? YES HIGH IMPEDANCE CHARGE PUMP YES REFERENCE EDGE AT PFD? YES RELEASE CHARGE PUMP HIGH IMPEDANCE YES DLD == HIGH The holdover function senses the logic level of the LD pin as a condition to enter holdover. The signal at LD can be from the DLD, ALD, or current source LD mode (CSDLD) ...

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... CLK FREQUENCY STATUS A/B PROGRAMMABLE N DELAY PRESCALER COUNTERS N DIVIDER ZERO DELAY BLOCK DIVIDE FROM CHANNEL DIVIDER Figure 35. Reference and VCO Status Monitors Rev Page AD9520-5 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV ...

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... Zero delay operation aligns the phase of the output clocks with the phase of the external PLL reference input. The zero delay function of the AD9520-5 is achieved by feeding the output of Channel Divider 0 back to the PLL N divider. In Figure 36, the change in signal routing for zero delay mode is shown in blue ...

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... VCO divider as the source to the distribution section, even if no channel uses it. Table 27. Routing VCO Divider Input Directly to the Outputs Register Setting 0x1E1[ 0x192[ 0x195[ 0x198[ 0x19B[ Rev Page AD9520-5 PLL DIVIDE CLOCK DISTRI- BUTION DISTRIBUTION ...

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... AD9520-5 Clock Frequency Division The total frequency division is a combination of the VCO divider (when used) and the channel divider. When the VCO divider is used, the total division from the CLK to the output is the product of the VCO divider ( and 6) and the division of the channel divider ...

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... Table 34. Setting Phase Offset and Division Start Divider High (SH) 0 0x191[4] 1 0x194[4] 2 0x197[4] 3 0x19A[4] Rev Page AD9520-5 D Output Duty Cycle X Disable Div DCC = 1 Disable Div DCC = 1)/ 50%, requires 1)/ 50%, requires 1 x%)/(2 × 3), ...

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... AD9520-5 Let Δ = delay (in seconds). t Δ = delay (in cycles of clock signal at input period of the clock signal at the input of the divider seconds). Φ × SH[ × PO[ × PO[ × PO[ × PO[0] The channel divide by is set high cycles and M = low cycles. Case 1 For Φ ...

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... Rev Page CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT CLOCKING AD9520-5 ...

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... AD9520-5 SW1B SW1A R2 R1 200Ω 200Ω N1 QN1 N2 QN2 SW2 4.4mA Figure 41. LVPECL Output Simplified Equivalent Circuit CMOS Output Drivers The user can also individually configure each LVPECL output as a pair of CMOS outputs, which provides CMOS outputs. When an output is configured as CMOS, CMOS Output A and CMOS Output B are automatically turned on ...

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... Powering down a clock channel also automatically powers down the drivers connected to it. The register map details the individual power-down settings for each output channel. These settings are found in 0x192[2], 0x195[2], 0x198[2], and 0x19B[2]. Rev Page AD9520-5 ...

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... AD9520-5 SERIAL CONTROL PORT The AD9520 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9520 serial control port is compatible with most synchronous transfer formats, including Philips I2C, Motorola® SPI®, and Intel® ...

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... A repeated start (Sr) condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. Rev Page AD9520-5 ACKNOWLEDGE FROM SLAVE-RECEIVER ...

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... AD9520-5 Data Transfer Format Send byte format—the send byte protocol is used to set up the register address for subsequent commands. S Slave Address W A Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address. ...

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... determined by W1:W0 the read operation is in streaming mode, continuing until CS is raised. Streaming mode does not skip over reserved or blank registers. The readback data is valid on the falling edge of SCLK. Rev Page AD9520-5 ...

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... AD9520-5 The default mode of the AD9520 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin also possible to set the AD9520 to unidirectional mode (0x000[ and 0x000[0] = 1). In unidirectional mode, the readback data appears on the SDO pin ...

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... D1 D0 REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA t C DON'T CARE DON'T CARE REGISTER ( DATA AD9520-5 LSB I0 A0 DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE ...

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... AD9520 SCLK SDIO Table 41. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of the clock CLK t Setup time between the CS falling edge and SCLK rising edge (start of communication cycle) ...

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... PLL configuration. There are two parts to the EEPROM buffer segment: register section definition groups and operational codes. Each register section definition group contains the starting address and number of bytes to be written to the EEPROM. Rev Page AD9520-5 ...

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... AD9520-5 If the AD9520 register map were continuous from Address 0x000 to Address 0x232, only one register section definition group would consist of a starting address of 0x000 and a length of 563 bytes. However, this is not the case. The AD9520 register map is noncontiguous, and the EEPROM is only 512 bytes long. ...

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... A where T is the ambient temperature (°C). A Values of θ are provided for package comparison and PCB JC design considerations when an external heat sink is required. Values of Ψ JB design considerations. Rev Page AD9520-5 Value (°C/W) 22.0 19.2 17.2 11.6 1.3 0.1 can be used for a first-order JA by the equation J × PD) ...

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... AD9520-5 REGISTER MAP Register addresses that are not listed in Table 44 are not used, and writing to those registers has no effect. The user should avoid writing values other than 00h to register addresses marked unused. Table 44. Register Map Overview Addr (Hex) Parameter Bit 7 (MSB) ...

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... Unused CSDLD En OUT11 Unused Divider 0 low cycles Divider 0 Divider 0 Divider 0 ignore force start SYNC high high Unused Rev Page AD9520-5 Bit 2 Bit 1 Bit 0 (LSB) Enable Unused zero delay REF2 REF1 freq > Digital lock freq > threshold detect threshold OUT0 LVPECL OUT0 ...

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... AD9520-5 Addr (Hex) Parameter Bit 7 (MSB) 193 Divider 1 (PECL) 194 Divider 1 bypass 195 196 Divider 2 (PECL) 197 Divider 2 bypass 198 199 Divider 3 (PECL) 19A Divider 3 bypass 19B 19C to 1DF VCO Divider and CLK Input 1E0 VCO divider 1E1 Input CLKs Unused ...

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... EEPROM Buffer Segment Register 10 (default: number of bytes for Group 4) EEPROM Buffer Segment Register 13 (default: number of bytes for Group 5) EEPROM Buffer Segment Register 16 (default: number of bytes for Group 6) EEPROM Buffer Segment Register 19 (default: number of bytes for Group 7) Rev Page AD9520-5 Bit 2 Bit 1 Bit 0 (LSB) Default ...

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... AD9520-5 Addr (Hex) Parameter Bit 7 (MSB) A14 EEPROM EEPROM Buffer Segment Register 21 (default: Bits[7:0] of starting register address for Group 7) Buffer Segment Register 21 A15 EEPROM Buffer Segment Register 22 A16 EEPROM Buffer Segment Register 23 A17 to AFF EEPROM Control B00 EEPROM status (read-only) B01 ...

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... EEPROM. It does not affect AD9520 operation in any way (default: 0x00). 16-bit EEPROM ID[15:8]. This register, along with 0x005, allows the user to store a unique ID to identify which version of the AD9520 register settings is stored in the EEPROM. It does not affect AD9520 operation in any way (default: 0x00). Rev Page AD9520 mode.) ...

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... AD9520-5 Table 48. PLL Reg. Addr (Hex) Bit(s) Name Description 010 [7] PFD polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO. [ positive (higher control voltage produces higher frequency) (default). [ negative (higher control voltage produces lower frequency). ...

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... LD pin comparator output (active high LVL VS (PLL power supply DYN REF1 clock (differential reference when in differential mode DYN REF2 clock (not available in differential mode DYN Selected reference to PLL (differential reference when in differential mode). Rev Page AD9520-5 ...

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... AD9520-5 Reg. Addr (Hex) Bit(s) Name Description [7] [6] [ 017 [1:0] Antibacklash [1] [0] Antibacklash Pulse Width (ns) pulse width 018 [7] Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost. ...

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... LVL Status of unselected reference (not available in differential mode); active low LVL Status of REF1 frequency (active low LVL Status of REF2 frequency (active low LVL (Status of REF1 frequency) AND (status of REF2 frequency). Rev Page AD9520-5 ...

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... AD9520-5 Reg. Addr (Hex) Bit(s) Name Description [5] [4] [ 01B [7] Enable CLK Enables or disables the external CLK frequency monitor. frequency [ disable the external CLK frequency monitor (default). monitor [ enable the external CLK frequency monitor. ...

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... AND (status of selected reference) AND (status of VCO LVL Status of CLK frequency (active low LVL Selected reference (low = REF2, high = REF1 LVL DLD; active low LVL Holdover active (active low LVL LD pin comparator output (active low). Rev Page AD9520-5 ...

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... AD9520-5 Reg. Addr (Hex) Bit(s) Name Description 01D [5] Enable clock Enable PLL reference input clock doubler. doubler [ doubler disabled (default). [ doubler enabled. 01D [4] Disable PLL Disables the PLL status register readback. status register [ PLL status register enabled (default). ...

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... Asynchronous power-down. 1 Asynchronously enable OUT7 if not powered down by other settings. To use this feature, the user must use current source digital lock detect and set the enable LD pin comparator bit (0x01D[3]). Rev Page AD9520-5 OUT0A OUT0B Noninverting Inverting Inverting Noninverting Noninverting ...

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... AD9520-5 Reg. Addr (Hex) Bit(s) Name Description 0FC [6] CSDLD En OUT6 OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [5] CSDLD En OUT5 OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [4] CSDLD En OUT4 OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. ...

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... Forces divider output to high. This requires that ignore SYNC also be set. [ divider output forced to low (default). [ divider output forced to high. Selects clock output to start high or start low. [ start low (default). [ start high. Phase offset(default: 0x0). Rev Page AD9520-5 ...

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... AD9520-5 Reg. Addr (Hex) Bit(s) Name 198 [2] Channel 2 power-down 198 [1] Channel 2 direct-to-output 198 [0] Disable Divider 2 DCC 199 [7:4] Divider 3 low cycles 199 [3:0] Divider 3 high cycles 19A [7] Divider 3 bypass 19A [6] Divider 3 ignore SYNC 19A [5] Divider 3 force high 19A [4] Divider 3 start high 19A ...

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... The soft SYNC bit works in the same way as the SYNC pin, except that the polarity of the bit is reversed; that is, a high level forces selected channels into a predetermined static state, and a 1-to-0 transition triggers a SYNC. [ same as SYNC high. [ same as SYNC low. Rev Page AD9520-5 Divide 2 (default ...

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... AD9520-5 Table 54. EEPROM Buffer Segment Reg. Addr (Hex) Bit(s) Name Description A00 to [7:0] EEPROM Buffer The EEPROM buffer segment section stores the starting address and number of bytes that are to be A16 Segment Register 1 stored and read back to and from the EEPROM. Because the AD9520 register space is noncontiguous, ...

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... LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue. In the case where VS_DRV = 2.5 V, the 50 Ω termination resistor connected to ground in Figure 59 should be changed to 19 Ω. Rev Page AD9520 SNR = 20log t 2πf ...

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... AD9520-5 Thevenin-equivalent termination uses a resistor network to provide 50 Ω termination voltage that is below V the LVPECL driver. In this case, VS_DRV on the AD9520 should equal V of the receiving buffer. Although the resistor S combination shown results bias point of VS_DRV − the actual common-mode voltage is VS_DRV − 1.3 V because there is additional current flowing from the AD9520 LVPECL driver through the pull-down resistor ...

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... Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Rev Page 0.60 MAX PIN 1 INDICATOR 64 1 6.35 EXPOSED PAD 6.20 SQ (BOTTOM VIEW) 6. 0.25 MIN 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-64-4 CP-64-4 AD9520-5 ...

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... AD9520-5 NOTES Rev Page ...

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... NOTES Rev Page AD9520-5 ...

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... AD9520-5 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07239-0-10/08(0) Rev Page ...