MAX3107_11 MAXIM [Maxim Integrated Products], MAX3107_11 Datasheet - Page 17

• Manufacturer Part Number: MAX3107_11
• Description: SPI/I2C UART with 128-Word FIFOs
• Manufacturer: MAXIM [Maxim Integrated Products]

Figure 6. Receive FIFO
Set CLKSource[4]: ClockEn to 1 and CLKSource[1]:
CrystalEn to 1 to enable and select the crystal oscilla-
tor. The on-chip crystal oscillator has load capacitances
of 20pF integrated in both XIN and XOUT. Connect an
external crystal or ceramic oscillator between XIN and
XOUT.
Figure 7. Clock Selection Diagram
CURRENT FILL LEVEL
I
2
C/SPI INTERFACE
LSR[5:2]
LSR[1]
LSR[0]
ISR[3]
ISR[6]
XOUT
OVERRUN
______________________________________________________________________________________
TIMEOUT
TRIGGER
ERRORS
EMPTY
XIN
FIFOTrgLvl[7:4]
RECEIVE FIFO
OSCILLATOR
RxFIFOLvl
CRYSTAL
WORD
SPI/I
RECEIVER
RHR
Crystal Oscillator
ERROR 128
CrystalEn
2
C UART with 128-Word FIFOs
4
3
2
1
RECEIVED
DATA
ClockEn
RX
When an external clock signal is used, this should
be connected to XIN. Leave XOUT unconnected.
Set CLKSource[4]: ClockEn to 1 and CLKSource[1]:
CrystalEn to 0 to select external clocking.
The internal predivider and PLL allow for a wide range
of external clock frequencies and baud rates. The PLL
can be configured to multiply the input clock rate by a
factor of 6, 48, 96, or 144 through PLLConfig[7:6]. The
predivider, located between the input clock and the PLL,
allows division of the input clock by a factor between 1
and 63 by writing to PLLConfig[5:0]. See the PLLConfig
register description for more information.
The internal fractional baud-rate generator provides a
high degree of flexibility and high resolution in baud-
rate programming. The baud-rate generator has a 16-bit
integer divisor and a 4-bit word for the fractional divisor.
The fractional baud-rate generator can be used with the
external crystal or clock source.
The integer and fractional divisors are calculated through
the divisor, D:
where f
rate generator and D is the ideal divisor. f
less than 96MHz. In 2x and 4x rate modes, replace the
divisor 16 by 8 or 4, respectively.
The integer divisor portion, DIV, of the divisor, D, is
obtained by truncating D:
DIVIDER
REF
PLLEn
is the reference frequency input to the baud-
PLL
Fractional Baud-Rate Generator
D
DIV = TRUNC(D)
PLLByps
=
16 BaudRate
×
f
REF
GENERATOR
BAUD-RATE
PLL and Predivider
External Clock Source
REF
must be
17