SY100E136JCTR MICREL [Micrel Semiconductor], SY100E136JCTR Datasheet - Page 6

• Manufacturer Part Number: SY100E136JCTR
• Description: 6-BIT UNIVERSAL UP/DOWN COUNTER
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel
(CL
reaches terminal count. Also note that both CL
carry-out pin (C
clock period. The input structure for look-ahead-carry-in
(CL
input. From the truth table one can see that both the C
and the CL
be enabled to count (either count up or count down). The
CL
order E136 and, therefore, are only asserted for a single
clock period. Since the CL
asserted one clock period prior to the C
count, its C
counter will be in the "LOW" state. This signals the given
counter that it will need to count one upon the next terminal
count of the least significant counter (LSC). The CL
output of the LSC will pulse low one clock period before it
reaches terminal count. This CL
into the CL
following positive clock transition. Since both C
are in the LOW state, the next clock pulse will cause the
least significant counter to roll over and all higher order
counters, if signaled by the C
is counting by one, the CL
presented by the CL
order counter will ripple through the chain to update the
Note from the waveforms that the look-ahead-carry output
The CL
If the counter previous to a given counter is at terminal
During the clock pulse in which the higher order counter
IN
OUT
IN
) and carry-in (C
inputs are driven by the CL
) pulses low one clock pulse before the counter
CL
CLK
IN
C
Figure 2. Look-Ahead-Carry Input Structure
IN
CLOCK
OUT
IN
IN
IN
input is registered and then OR'ed with the C
inputs must be in a LOW state for the E136 to
Figure 3. 6-bit Programmable Divider
input of the higher order counters on the
OUT
output, and thus the C
D
) of the device pulse low for only one
OUT
IN
) is pictured in Figure 2.
of the LSC. The C
Q
IN
IN
CLK
IN
input is registered, it must be
is clocking in the high signal
Q
D
inputs, to count by one.
0
0
– Q
– D
OUT
OUT
C
C
5
5
OUT
OUT
signal will be clocked
S
S
IN
IN
output of the lower
0
1
input.
input of the given
ACTIVE
LOW
IN
s in the higher
"LO"
OUT
IN
and CL
and the
OUT
IN
IN
IN
6
count status for the next occurrence of terminal count on
the LSC. This ripple propagation will not affect the count
frequency as it has 2
without affecting the count operation of the chain.
frequency of the chain as compared to a free running single
device will be the set-up time of the CL
will consist of the CLK to CL
CL
the CL
Programmable Divider
be configured as a programmable divider. Figure 3 illustrates
the configuration for a 6-bit count-down programmable
divider. If for some reason a count-up divider is preferred,
the C
Examination of the truth table for the E136 shows that when
both S
the next positive transition of the clock. If the S
low and the S
count-down mode and will count towards an all zero state
upon successive clock pulses.
operation of the C
build programmable dividers.
predesignated number into the counter and count to terminal
count. Upon terminal count, the counter should automatically
reload the divide number. With the architecture shown in
Figure 3, when the counter reaches terminal count, the
C
combined with the low on S
the inputs present on D
into the counter, C
longer at terminal count, thereby placing the counter back
into the count mode.
OUT
Divide
The only limiting factor which could reduce the count
Using external feedback of the C
For a programmable divider, one must to load a
IN
Ratio
36
37
38
62
63
64
2
3
4
5
*
*
*
*
set-up time, plus any path length differences between
OUT
output, and thus the S
OUT
1
and S
signal is simply fed back to S
output and the clock.
Table 1. Preset Inputs Versus Divide Ratio
D5
H
H
H
H
H
H
L
L
L
L
*
*
*
*
2
1
are LOW, the counter will parallel load on
input is high, the counter will be in the
OUT
OUT
6
-1 or 63 clock pulses to ripple through
D4
output, it becomes a trivial matter to
H
H
H
L
L
L
L
L
L
L
0
*
*
*
*
–D
will go HIGH as the counter is no
Preset Data Inputs
5
2
OUT
. Upon loading the divide value
will cause the counter to load
D3
1
H
H
H
L
L
L
L
L
L
L
*
*
*
*
input, will go LOW. This,
delay of the E136, plus the
Knowing this and the
OUT
D2
H
H
H
H
H
H
L
L
L
L
*
*
*
*
IN
pin, the E136 can
2
input. This limit
rather than S
D1
H
H
H
H
H
L
L
L
L
L
*
*
*
*
SY100E136
SY10E136
2
input is
D0
H
H
H
H
H
H
L
L
L
L
*
*
*
*
1
.