CAT25256 ONSEMI [ON Semiconductor], CAT25256 Datasheet - Page 9

• Manufacturer Part Number: CAT25256
• Description: 256-Kb SPI Serial CMOS EEPROM
• Manufacturer: ONSEMI [ON Semiconductor]

Read from Memory Array
followed by a 16−bit address (see Table 11 for the number
of significant address bits).
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
SCK
SCK
To read from memory, the host sends a READ instruction
After receiving the last address bit, the CAT25256 will
CS
CS
SO
SO
SI
SI
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
Dashed Line = mode (1, 1)
0
0
0
0
0
1
0
0
2
1
0
3
HIGH IMPEDANCE
OPCODE
OPCODE
0
2
0
4
0
0
HIGH IMPEDANCE
5
3
1
6
0
4
1
7
A
N
8
1
5
Figure 10. RDSR Timing
Figure 9. READ Timing
READ OPERATIONS
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9
BYTE ADDRESS*
6
0
10
1
9
7
20
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Status Register
command. After receiving the last bit of the command, the
CAT25256 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at
any time, including during an internal write cycle. While the
internal write cycle is in progress, the RDSR command will
output the RDY (Ready) bit status only (i.e., data out = FFh).
MSB
21
To read the status register, the host simply sends a RDSR
8
7
22 23 24 25 26 27 28 29
9
6
A
0
10
5
MSB
7
11
6
4
DATA OUT
5
12
3
DATA OUT
4
3
13
2
2
14
30
1
1
0
0