CAT25640 CATALYST [Catalyst Semiconductor], CAT25640 Datasheet - Page 4

• Manufacturer Part Number: CAT25640
• Description: 64-Kb SPI Serial CMOS EEPROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

CAT25640
PIN DESCRIPTION
SI: The serial data input pin accepts op-codes,
addresses and data. In SPI modes (0,0) and (1,1)
input data is latched on the rising edge of the SCK
clock input.
SO: The serial data output pin is used to transfer data
out of the device. In SPI modes (0,0) and (1,1) data is
shifted out on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT25640.
CS
enable/disable the CAT25640. When CS
SO output is tri-stated (high impedance) and the
device is in Standby Mode (unless an internal write
operation is in progress). Every communication
session between host and CAT25640 must be
preceded by a high to low transition and concluded
with a low to high transition of the CS
¯¯¯ : The write protect input pin will allow all write
WP
operations to the device when held high. When WP
pin is tied low and the WPEN bit in the Status
Register (refer to Status Register description, later in
this Data Sheet) is set to “1”, writing to the Status
Register is disabled.
¯¯¯¯¯ : The HOLD
HOLD
mission between host and CAT25640, without
having to retransmit the entire sequence at a later
time. To pause, HOLD
resume it must be taken back high, with the SCK
input low during both transitions. When not used for
pausing, the HOLD
either directly or through a resistor.
Figure 1. Synchronous Data Timing
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1128 Rev. B
¯¯ : The chip select input pin is used to
SCK
CS
SO
SI
V
V
V
V
V
V
IH
V
V IL
OH
OL
IL
IH
IL
IH
¯¯¯¯¯ input pin is used to pause trans–
¯¯¯¯¯ input should be tied to V
HI-Z
¯¯¯¯¯ must be taken low and to
t
SU
VALID IN
¯¯ input.
¯¯ is high, the
t
CSS
t
WH
t
H
¯¯¯
CC
,
4
FUNCTIONAL DESCRIPTION
The CAT25640 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8-bit instruction register. The
instruction set and associated op-codes are listed in
Table 1.
Reading data stored in the CAT25640 is accomplished
by simply providing the READ command and an
address. Writing to the CAT25640, in addition to a
WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits
in a Status Register, as will be explained later.
After a high to low transition on the CS
CAT25640 will accept any one of the six instruction op-
codes listed in Table 1 and will ignore all other possible
8-bit combinations. The communication protocol follows
the timing from Figure 1.
Table 1: Instruction Set
t
WL
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
t
V
t
t FI
RI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Opcode
t
HO
Characteristics subject to change without notice
t
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
CSH
t
DIS
© Catalyst Semiconductor, Inc.
¯¯ input pin, the
HI-Z
t
CS