SY100E417JCTR MICREL [Micrel Semiconductor], SY100E417JCTR Datasheet
SY100E417JCTR
Manufacturer Part Number
SY100E417JCTR
Description
QUINT LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR
Manufacturer
MICREL [Micrel Semiconductor]
Datasheet
1.SY100E417JCTR.pdf
(5 pages)
FEATURES
BLOCK DIAGRAM
3.3V and 5V power supplies required
Also, supports LVPECL-to-PECL translation
500ps propagation delays
Fully differential design
Differential line receiver capability
Available in 28-pin PLCC package
FUNCTION TABLE
PECL-to-LVPECL
LVPECL-to-PECL
PECL-to-PECL
LVPECL-to-LVPECL
Function
V
D
D
D
D
D
D
D
D
D
D
BB
0
0
1
1
2
2
3
3
4
4
5.0V
5.0V
5.0V
5.0V
Vcc
Vcco
3.3V
5.0V
5.0V
3.3V
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
0
1
1
2
2
3
3
4
4
QUINT LVPECL-TO-PECL
OR PECL-TO-LVPECL
TRANSLATOR
Vcc_V
5.0V
3.3V
5.0V
3.3V
BB
1
It can also be used as a quint PECL-to-LVPECL translator.
The device receives standard PECL signals and translates
them to differential LVPECL output signals (or vice versa).
receiver for PECL-to-PECL or LVPECL-to-LVPECL signals.
However, please note that for the latter we will need two
different power supplies. Please refer to Function Table for
more details.
input signals. If a single ended input is to be used, the V
output should be connected to the Dn input and the active
signal will drive the Dn input. When used, the V
be bypassed to V
designed to act as a switching reference for the SY100E417
under single ended input conditions. As a result, the pin
can only source/sink 0.5mA of current.
the SY100E417 requires three power rails. The V
V
supply, the 3.3V supply is to be connected to the V
supply, and GND is connected to the system ground plane.
Both the V
a 0.01 F capacitor.
the SY100E417 requires three power rails as well. The 5.0V
supply is connected to the V
is connected to the V
the system ground plane. V
proper V
V
input. For differential LVPECL input, V
3.3V or 5.0V.
at a V
GND. This condition will force the "Qn" output low, ensuring
stability.
CC
CC
DESCRIPTION
The SY100E417 is a quint LVPECL-to-PECL translator.
The SY100E417 can also be used as a differential line
A V
To accomplish the PECL-to-LVPECL level translation,
To accomplish the LVPECL-to-PECL level translation,
Under open input conditions, the Dn input will be biased
_V
_V
CC
BB
BB
BB
/2 voltage level and the Dn input will be pulled to
BB
= 3.3V is only required for single-ended LVPECL
supply is to be connected to the standard PECL
output is provided for interfacing single ended
CC
output level if a single ended input is used.
and V
CC
CCO
CC
via a 0.01 F capacitor. The V
_V
should be bypassed to ground with
BB
CC
CC
pin and GND is connected to
and V
_V
BB
CCO
is used to provide a
CC
_V
Rev.: B
Issue Date: March, 1999
pins, 3.3V supply
SY100E417
BB
can be either
Amendment: /1
BB
CC
should
BB
CCO
and
BB
is
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SY100E417JCTR Summary of contents
Page 1
FEATURES 3.3V and 5V power supplies required Also, supports LVPECL-to-PECL translation 500ps propagation delays Fully differential design Differential line receiver capability Available in 28-pin PLCC package BLOCK DIAGRAM ...
Page 2
Micrel PIN CONFIGURATION TOP VIEW GND 1 PLCC J28 ...
Page 3
Micrel LVPECL OUTPUT DC ELECTRICAL CHARACTERISTICS V = +4.5V to +5.5V +3.0V to 3.8V CC CCO Symbol Parameter V Power Supply Voltage CCO (1) V Output HIGH Voltage OH (1) V Output LOW Voltage OL I Power Supply ...
Page 4
... The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V PRODUCT ORDERING CODE Ordering Package Code Type SY100E417JC J28-1 SY100E417JCTR J28 – Min. ...
Page 5
Micrel 28 LEAD PLCC (J28-1) MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 TEL This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for ...