CY7C1480BV33_11 CYPRESS [Cypress Semiconductor], CY7C1480BV33_11 Datasheet
CY7C1480BV33_11
Related parts for CY7C1480BV33_11
CY7C1480BV33_11 Summary of contents
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M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined ...
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Logic Block Diagram – CY7C1480BV33 (2 M × 36 A1, A ADDRESS REGISTER MODE ADV CLK ADSC ADSP BYTE BW D WRITE REGISTER BYTE BW C ...
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Logic Block Diagram – CY7C1486BV33 (1 M × 72) ADDRESS A 0, A1,A REGISTER MODE ADV CLK ADSC ADSP DQ , DQP WRITE DRIVER DQP WRITE DRIVER DQ , DQP ...
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Contents Pin Configurations ........................................................... 5 Pin Definitions .................................................................. 8 Functional Overview ........................................................ 9 Single Read Accesses ................................................ 9 Single Write Accesses Initiated by ADSP ................... 9 Single Write Accesses Initiated by ADSC ................. 10 Burst Sequences ....................................................... 10 Sleep Mode ...
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Pin Configurations Figure 1. CY7C1480BV33 100-pin TQFP Pinout DQP DQc DDQ V 5 SSQ SSQ V DDQ 11 ...
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Pin Configurations (continued) 165-ball FBGA (15 × 17 × 1.4 mm) Pinout NC/288M NC/144M A CE2 C DQP DDQ DDQ ...
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Pin Configurations (continued) 209-ball FBGA (14 × 22 × 1.76 mm) Pinout BWS BWS ...
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Pin Definitions Pin Name I Input Synchronous Input- BW ,BW ,BW , Synchronous BW ,BW ,BW , Input- Synchronous BWE Input- Synchronous CLK ...
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Pin Definitions (continued) Pin Name I/O V I/O power supply Power supply for the I/O circuitry. DDQ MODE Input static TDO JTAG serial output synchronous TDI JTAG serial input synchronous TMS JTAG serial input synchronous TCK JTAG clock NC – ...
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DQs inputs. Doing so tri-states the output drivers safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when ...
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Truth Table The truth table for CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 follows. Operation Add. Used Deselect cycle, power-down None Deselect cycle, power-down None Deselect cycle, power-down None Deselect cycle, power-down None Deselect cycle, power-down None Sleep mode, power-down None Read cycle, ...
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Truth Table for Read/Write The read/write truth table for CY7C1480BV33 follows. Function (CY7C1480BV33) Read Read Write byte A – (DQ and DQP ) A A Write byte B – (DQ and DQP ) B B Write bytes B, A Write ...
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IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full ...
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TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Codes on page 19. Three of these instructions are listed as RESERVED and must not be used. The other five instructions ...
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TAP Controller State Diagram TEST-LOGIC 1 RESET 0 RUN-TEST/ 0 IDLE Document Number: 001-15145 Rev. *F CY7C1480BV33, CY7C1482BV33, CY7C1486BV33 1 1 SELECT DR-SCA CAPTURE-DR 0 SHIFT- EXIT1-DR 0 PAUSE- EXIT2-DR 1 ...
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TAP Controller Block Diagram TDI TCK TM S Document Number: 001-15145 Rev. *F CY7C1480BV33, CY7C1482BV33, CY7C1486BV33 0 Bypass Register Selection Instruction Register Circuitry Identification Register ...
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TAP AC Test Conditions Input pulse levels................................................V Input rise and fall times....................................................1 ns Input timing reference levels.......................................... 1.5 V Output reference levels ................................................. 1.5 V Test load termination supply voltage ............................. 1.5 V 3.3-V TAP AC Output Load Equivalent ...
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TAP AC Switching Characteristics [9, 10] Over the Operating Range Parameter Clock t TCK clock cycle time TCYC t TCK clock frequency TF t TCK clock HIGH time TH t TCK clock LOW time TL Output Times t TCK clock ...
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Identification Register Definitions CY7C1480BV33 Instruction Field (2 M × 36) Revision number (31:29) Device depth (28:24) Architecture/Memory type(23:18) 000000 Bus width/density(17:12) 100100 Cypress JEDEC ID Code (11:1) 00000110100 ID register presence indicator (0) Scan Register Sizes Register Name Instruction Bypass ...
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Boundary Scan Exit Order (2 M × 36) Bit # 165-ball ID Bit # ...
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Boundary Scan Exit Order (1 M × 72) Bit # 209-ball ID Bit # ...
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Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature................................. –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Supply voltage on V ...
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Electrical Characteristics [11, 12] Over the Operating Range (continued) Parameter Description I Automatic CE power-down SB2 current—CMOS inputs I Automatic CE power-down SB3 current—CMOS inputs I Automatic CE power-down SB4 current—TTL inputs Capacitance Tested initially and after any design or ...
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V I/O Test Load OUTPUT OUTPUT = 50 Ω Ω 1 (a) 2.5 V I/O Test Load OUTPUT OUTPUT = 50 Ω Ω ...
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Switching Characteristics [14, 15] Over the Operating Range Parameter Description t V (typical) to the first access POWER DD Clock t Clock cycle time CYC t Clock HIGH CH t Clock LOW CL Output Times t Data output valid after ...
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Switching Waveforms [18] Figure 3 shows read cycle timing. t CYC CLK ADH ADS ADSP t ADS t ADH ADSC ADDRESS WES t WEH GW, BWE, BWx ...
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Switching Waveforms (continued) [19, 20] Figure 4 shows write cycle timing. t CYC CLK ADS t ADH ADSP t ADS t ADH ADSC ADDRESS A1 Byte write signals are ignored for ...
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Switching Waveforms (continued) [21, 22, 23] Figure 5 shows read-write cycle timing. t CYC CLK ADS t ADH ADSP ADSC ADDRESS BWE CES t CEH CE ...
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Switching Waveforms (continued) [24, 25] Figure 6 shows ZZ mode timing. CLK ZZI I SUPPLY I DDZZ ALL INPUTS (except ZZ) Outputs (Q) Notes 24. Device must be deselected when entering ZZ mode. See the section ...
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Ordering Information Table 1 lists the key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, ...
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Package Diagrams Document Number: 001-15145 Rev. *F CY7C1480BV33, CY7C1482BV33, CY7C1486BV33 Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) 51-85050 *D Page [+] Feedback ...
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Package Diagrams (continued) Figure 8. 165-ball FBGA (15 × 17 × 1.4 mm) Document Number: 001-15145 Rev. *F CY7C1480BV33, CY7C1482BV33, CY7C1486BV33 51-85165 *C Page [+] Feedback ...
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Package Diagrams (continued) Figure 9. 209-ball FBGA (14 × 22 × 1.76 mm) Document Number: 001-15145 Rev. *F CY7C1480BV33, CY7C1482BV33, CY7C1486BV33 51-85167 *A Page [+] Feedback ...
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Reference Information Acronyms Table 2. Acronyms Acronym Description FBGA fine-pitch ball grid array I/O input/output JTAG joint test action group LSB least significant bit MSB most significant bit PLL phase-locked loop SRAM static random access memory TAP test access port ...
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Document History Page Document Title: CY7C1480BV33/CY7C1482BV33/CY7C1486BV33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM Document Number: 001-15145 Orig. of Submission Revision ECN Change ** 1024385 VKN/KKVTMP *A 2183566 VKN/PYRS *B 2898663 NJY *C 2905654 ...
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