CAT25M01 ONSEMI [ON Semiconductor], CAT25M01 Datasheet
CAT25M01
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CAT25M01 Summary of contents
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... CAT25M01 1 Mb SPI Serial CMOS EEPROM Description The CAT25M01 is a 1M−bit Serial CMOS EEPROM device internally organized as 128Kx8 bits. This features a 256−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines ...
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Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating ...
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Table 4. PIN CAPACITANCE (T = 25° 1.0 MHz Symbol C Output Capacitance (SO) OUT C Input Capacitance (CS, SCK, SI, WP, HOLD These parameters are tested initially and after a design or process ...
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... CAT25M01. CS: The chip select input pin is used to enable/disable the CAT25M01. When CS is high, the SO output is tri−stated (high impedance) and the device is in Standby Mode (unless an internal write operation is in progress). Every ...
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Status Register The Status Register, as shown in Table 8, contains a number of status and control bits. The RDY (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during ...
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... The internal Write Enable Latch and the correspon–ding Status Register WEL bit are set by sending the WREN instruction to the CAT25M01. Care must be taken to take the CS input high after the WREN instruction, as otherwise the Write Enable Latch will not be properly set. WREN timing is illustrated in Figure 3 ...
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... Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 24−bit address and a data byte as shown in Figure 5. Only 17 significant address bits are used by the CAT25M01. The rest are don’t care bits, as shown in Table 11. Internal programming will start after the low to high CS transition. During an internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored ...
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Write Status Register The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits and 7 can be written using the WRSR command ...
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... To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAT25M01 will shift out the contents of the status register on the SO pin (Figure 10). The status register may be read at any time, including during an internal write cycle. ...
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... POR trigger level. This bi−directional POR behavior protects the device against ‘brown−out’ failure following a temporary loss of power. The CAT25M01 device powers write disable state and in a low power standby mode. A WREN instruction must be issued prior any writes to the device. ...
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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
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PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL ...
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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
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... CAT25M01XI−T2 25M01A CAT25M01YI−GT3 SM1A CAT25M01YE−GT3 SM1A 10. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 11. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ...