CAT28C16A CATALYST [Catalyst Semiconductor], CAT28C16A Datasheet - Page 7

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CAT28C16A

Manufacturer Part Number
CAT28C16A
Description
16K-Bit CMOS PARALLEL E2PROM
Manufacturer
CATALYST [Catalyst Semiconductor]
Datasheet

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Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
Figure 5. Byte Write Cycle [CE Controlled]
Figure 6. DATA Polling
ADDRESS
ADDRESS
DATA OUT
DATA IN
I/O 7
WE
OE
WE
CE
OE
CE
t CS
t AS
D IN = X
t OES
t AH
t OEH
t CW
t DS
DATA VALID
HIGH-Z
D OUT = X
7
t OE
t WC
t OEH
t CH
DATA Polling
DATA polling is provided to indicate the completion of a
byte write cycle. Once a byte write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O
minate) until the programming cycle is complete. Upon
completion of the self-timed byte write cycle, all I/O’s will
output true data during a read cycle.
t DL
t DH
D OUT = X
t WC
7
(I/O
t OES
0
–I/O
Doc. No. 25033-00 2/98
6
are indeter-
5089 FHD F07
28C16A F08

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