CAT28F001 CATALYST [Catalyst Semiconductor], CAT28F001 Datasheet

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CAT28F001

Manufacturer Part Number
CAT28F001
Description
1 Megabit CMOS Boot Block Flash Memory
Manufacturer
CATALYST [Catalyst Semiconductor]
Datasheet

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CAT28F001
1 Megabit CMOS Boot Block Flash Memory
BLOCK DIAGRAM
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
DESCRIPTION
The CAT28F001 is a high speed 128K X 8 bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after sale
code updates.
The CAT28F001 has a blocked architecture with one 8
KB Boot Block, two 4 KB Parameter Blocks and one 112
KB Main Block. The Boot Block section can be at the top
or bottom of the memory map and includes a reprogram-
ming write lock out feature to guarantee data integrity. It
is designed to contain secure code which will bring up
the system minimally and download code to other loca-
tions of CAT28F001.
FEATURES
Temperature Ranges
Fast Read Access Time: 70/90/120/150 ns
On-Chip Address and Data Latches
Blocked Architecture
— One 8 KB Boot Block w/ Lock Out
— Two 4 KB Parameter Blocks
— One 112 KB Main Block
Low Power CMOS Operation
12.0V
Automated Program & Erase Algorithms
High Speed Programming
Commercial, Industrial and Automotive
• Top or Bottom Locations
5% Programming and Erase Voltage
A 0 –A 16
WE
RP
CE
OE
WRITE STATE
VOLTAGE VERIFY
MACHINE
COMMAND
REGISTER
SWITCH
PROGRAM VOLTAGE
COUNTER
ADDRESS
SWITCH
Y-DECODER
X-DECODER
ERASE VOLTAGE
1
SWITCH
The CAT28F001 is designed with a signature mode
which allows the user to identify the IC manufacturer and
device type. The CAT28F001 is also designed with on-
Chip Address Latches, Data Latches, Programming and
Erase Algorithms.
The CAT28F001 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, PLCC or TSOP packages.
CE, OE LOGIC
Deep Powerdown Mode
— 0.05 A I
— 0.8 A I
Hardware Data Protection
Electronic Signature
100,000 Program/Erase Cycles and 10 Year
Data Retention
JEDEC Standard Pinouts:
— 32 pin DIP
— 32 pin PLCC
— 32 pin TSOP
Reset/Deep Power Down Mode
4K-BYTE PARAMETER BLOCK
4K-BYTE PARAMETER BLOCK
112K-BYTE MAIN BLOCK
8K-BYTE BOOT BLOCK
PP
CC
LATCH
DATA
Typical
I/O BUFFERS
Typical
I/O 0 –I/O 7
Y-GATING
SENSE
AMP
second source
Licensed Intel
REGISTER
STATUS
Doc. No. 25071-00 2/98 F-1
28F001 F01

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