CY7C1518AV18-278BZI CYPRESS [Cypress Semiconductor], CY7C1518AV18-278BZI Datasheet - Page 7

• Manufacturer Part Number: CY7C1518AV18-278BZI
• Description: 72-Mbit DDR-II SRAM 2-Word Burst Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Document Number: 001-06982 Rev. *C
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC/144M
NC/288M
V
V
V
V
Pin Name
REF
DD
SS
DDQ
Power Supply Power supply Inputs to the Core of the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
Reference
Ground
Output
Input-
Input
Input
Input
Input
Input
Input
Input
N/A
IO
(continued)
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
between ZQ and ground. Alternatively, this pin can be connected directly to V
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in DDR-I
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with DDR-I timing.
TDO for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Ground for the device.
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
Pin Description
CY7C1516AV18, CY7C1527AV18
CY7C1518AV18, CY7C1520AV18
DDQ
, which enables the
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