LV8111V_0910 SANYO [Sanyo Semicon Device], LV8111V_0910 Datasheet - Page 3

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LV8111V_0910

Manufacturer Part Number
LV8111V_0910
Description
For Polygon Mirror Motor 3-phase Brushless Motor Driver
Manufacturer
SANYO [Sanyo Semicon Device]
Datasheet
Continued from preceding page.
* Design target value, Do not measurement.
FG Output
Output ON resistance
Output leakage current
PWM Oscillator
High level output voltage
Low level output voltage
External capacitor charge current
Oscillation frequency
Amplitude
Recommended operation frequency
range
CSD Oscillation Circuit
High level output voltage
Low level output voltage
Amplitude
External capacitor charge current
External Capacitor Discharge Current
Oscillation frequency
Phase comparing output
Output ON resistance (high level)
Output ON resistance (low level)
Phase Lock Detection Output
Output ON resistance
Output leakage current
Error Amplifier Block
Input offset voltage
Input bias current
High level output voltage
Low level output voltage
DC bias level
Current Control Circuit
Drive gain
Current Limiter Circuit (pins RF and RFS)
Limiter voltage
Under-voltage Protection
Operation voltage
Hyteresis
CLD Circuit
External capacitor charge current
Operation voltage
Thermal Shutdown Operation
Thermal shutdown operation
temperature
Hysteresis
CLK pin
External input frequency
High level input voltage
Low level input voltage
Input open voltage
Hysteresis
High level input current
Low level input current
Parameter
V OL (FG)
I L (FG)
V OH (PWM)
V OL (PWM)
I CHG (PWM)
f(PWM)
V(PWM)
f OPR
V OH (CSD)
V OL (CSD)
V(CSD)
I CHG 1(CSD) V CHG 1 = 2.0V
I CHG 2(CSD) V CHG 2 = 2.0V
f(CSD)
V PDH
V PDL
V OL (LD)
I L (LD)
V IO (ER)
I B (ER)
V OH (ER)
V OL (ER)
V B (ER)
GDF
V RF
VSD
ΔVSD
I CLD
V H (CLD)
TSD
ΔTSD
f I (CLK)
V IH (CLK)
V IL (CLK)
V IO (CLK)
V IS (CLK)
I IH (CLK)
I IL (CLK)
Symbol
I FG = 7mA
V O = 5V
V PWM = 2V
C = 150pF
C = 0.068μF, Design target value *
I OH = -100μA
I OL = 100μA
I LD = 10mA
V O = 5V
I OH = -100μA
I OL = 100μA
V CLD = 0V
V CLK = VREG
Design target value *
While phase locked
Design target value (Junction temperature)
Design target value (Junction temperature)
V CLK = 0V
LV8111V
Conditions
VREG-0.5
EI-1.75
min
EI+0.7
0.465
2.95
1.75
3.25
-110
-5%
-4.5
180
150
-90
-14
-10
-10
1.3
1.5
2.7
0.8
0.5
8.3
0.2
0.1
2.0
0.2
15
30
-1
8
0
Ratings
VREG/2
EI+0.85
typ
EI-1.6
0.515
0.55
0.35
225
500
500
-3.0
175
-70
-10
-85
3.2
1.5
1.7
3.0
1.0
2.0
8.7
3.5
0.3
Continued on next page.
20
40
20
30
11
0
EI-1.45
max
EI+1.0
VREG
VREG
0.565
3.45
2.25
3.75
No.A1416-3/13
-1.5
270
300
700
700
+10
+10
1.7
-50
1.9
3.3
1.2
5%
0.6
9.1
0.5
1.0
0.4
-60
+1
30
10
14
50
30
10
10
-6
times
Vp-p
Vp-p
Unit
kHz
kHz
kHz
mV
°C.
μA
μA
μA
μA
μA
μA
μA
μA
μA
Hz
°C
Ω
Ω
Ω
Ω
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

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