MAX9206EAv MAXIM [Maxim Integrated Products], MAX9206EAv Datasheet
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MAX9206EAv
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MAX9206EAv Summary of contents
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Rev 2; 11/10 General Description The MAX9206/MAX9208 deserializers transform a high- speed serial bus low-voltage differential signaling (BLVDS) data stream into 10-bit-wide parallel LVCMOS/ LVTTL data and clock. The deserializers pair with seri- alizers such as the MAX9205/MAX9207, which ...
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Bus LVDS Deserializers ABSOLUTE MAXIMUM RATINGS AVCC, DVCC to AGND, DGND................................-0.3V to +4V RI+, RI- to AGND, DGND .........................................-0.3V to +4V All Other Pins to DGND ..............................-0. ROUT_ Short-Circuit Duration (Note 1) ......................Continuous Continuous Power Dissipation (T ...
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AC ELECTRICAL CHARACTERISTICS ( +3.0V to +3.6V, differential input voltage AVCC DVCC | | - -40°C to +85°C, unless otherwise noted. Typical values are +25°C.) (Notes ...
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Bus LVDS Deserializers AC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V, differential input voltage AVCC DVCC | | - -40°C to +85°C, unless otherwise noted. Typical values are ...
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PIN NAME 1, 12, 13 AGND Analog Ground Recovered Clock Strobe Edge Select. LVTTL/LVCMOS level input. Drive RCLK_ R/F high to strobe 2 RCLK_R/F ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling ...
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Bus LVDS Deserializers IN2 V - 0.3V CC RI+ R IN1 R IN1 RI- Figure 2. Input Fail-Safe Circuit START SYMBOL N BIT RCLK ROUT_ Figure 4. Input-to-Output Delay RCLK RCLK_R/F = ...
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PWRDN REFCLK t RFCP RI t ZHLK LOCK HIGH-Z RCLK HIGH-Z ROUT_ HIGH-Z 2048 x t Figure 7. PLL Lock Time from PWRDN REFCLK t RFCP RI LOCK RCLK ROUT_ Figure 8. Deserializer PLL Lock Time from _______________________________________________________________________________________ 10-Bit Bus ...
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Bus LVDS Deserializers Detailed Description The MAX9206/MAX9208 deserialize a BLVDS serializ- er's output into 10-bit wide parallel LVCMOS/LVTTL data and a parallel rate clock. The MAX9206/MAX9208 include a PLL that locks to the frequency and phase of the serial ...
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Table 1. Typical Lock Times REFCLK 16MHz FREQUENCY DATA PSEUDORANDOM PATTERN DATA Maximum 0.749µs Maximum (Clock 11.99 Cycles) Average 0.318µs Average (Clock 5.09 Cycles) Minimum 0.13µs Minimum (Clock 2.08 Cycles) Note: Pseudorandom lock performed with PRBS pattern, ...
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Bus LVDS Deserializers t /12 RCP Figure 9. Input Jitter Tolerance Applications Information Power-Supply Bypassing Bypass each supply pin with high-frequency surface- mount ceramic 0.1µF and 0.001µF capacitors in paral- lel as close to the ...
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Table 2. Input/Output Function Table LOGIC INPUTS CONDITIONS PWRDN REN X Low Power applied and stable Low High Deserializer initialized High High Deserializer initialized X = Don’t care. The MAX9206/MAX9208 deserializers can operate in a variety of topologies. Examples of ...
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Bus LVDS Deserializers REVISION REVISION NUMBER DATE 0 8/01 Initial release Max clock frequency increased to 45MHz; min values decreased for REFCLK and 1 12/07 RCLK period; updated package outline; updated names for pins 2 and 3. 2 11/10 ...