ADF4150 AD [Analog Devices], ADF4150 Datasheet - Page 12

• Manufacturer Part Number: ADF4150
• Description: Fractional-N/Integer-N PLL Synthesizer
• Manufacturer: AD [Analog Devices]

ADF4150
MUXOUT AND LOCK DETECT
The output multiplexer on the
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (for details, see
Figure 22). Figure 17 shows the MUXOUT section in block
diagram form.
INPUT SHIFT REGISTERS
The
a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of six latches
on the rising edge of LE. The destination latch is determined
by the state of the three control bits (C3, C2, and C1) in the
shift register. These are the 3 LSBs, DB2, DB1, and DB0, as
shown in Figure 2. The truth table for these bits is shown in
Table 5. Figure 19 shows a summary of how the latches are
programmed.
Table 5. C3, C2, and C1 Truth Table
C3
0
0
0
0
1
1
ANALOG LOCK DETECT
THREE-STATE-OUTPUT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
ADF4150
Control Bits
RESERVED
C2
0
0
1
1
0
0
digital section includes a 10-bit RF R counter,
DGND
DV
DD
Figure 17. MUXOUT Schematic
R COUNTER INPUT
C1
0
1
0
1
0
1
MUX
ADF4150
CONTROL
Register
Register 0 (R0)
Register 1 (R1)
Register 2 (R2)
Register 3 (R3)
Register 4 (R4)
Register 5 (R5)
allows the user
D
DV
GND
DD
MUXOUT
Rev. 0 | Page 12 of 28
PROGRAM MODES
Figure 20 through Figure 25 show how the program modes are
to be set up in the ADF4150.
A number of settings in the
These include the modulus value, phase value, R counter
value, reference doubler, reference divide-by-2, and current
setting. This means that two events have to occur before the
part uses a new value of any of the double-buffered settings.
First, the new value is latched into the device by writing to the
appropriate register. Second, a new write must be performed
on Register R0. For example, any time the modulus value is
updated, Register R0 must be written to, thus ensuring the
modulus value is loaded correctly. Divider select in Register 4
(R4) is also double buffered, but only if DB13 of Register 2 (R2)
is high.
OUTPUT STAGE
The RF
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 18. To allow the user
to optimize the power dissipation vs. the output power require-
ments, the tail current of the differential pair is programmable
by Bit D2 and Bit D1 in Register 4 (R4). Four current levels may
be set. These levels give output power levels of −4 dBm, −1 dBm,
+2 dBm, and +5 dBm, respectively, using a 50 Ω resistor to
AV
outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section). If the
outputs are used individually, the optimum output stage
consists of a shunt inductor to AV
Another feature of the
to the RF output stage can be shut down until the part
achieves lock as measured by the digital lock detect circuitry.
This is enabled by the mute-till-lock detect (MTLD) bit in
Register 4 (R4).
DD
and ac coupling into a 50 Ω load. Alternatively, both
OUT
+ and RF
VCO
OUT
DIVIDE-BY-1/
-2/-4/-8/-16
BUFFER/
Figure 18. Output Stage
− pins of the
ADF4150
ADF4150
is that the supply current
RF
DD
ADF4150
OUT
.
are double buffered.
+
RF
OUT
are connected
–