CY7C4201 CYPRESS [Cypress Semiconductor], CY7C4201 Datasheet - Page 10

• Manufacturer Part Number: CY7C4201
• Description: 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06016 Rev. *A
Switching Waveforms
Notes:
First Data Word Latency after Reset with Simultaneous Read and Write
Empty Flag Timing
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
19. When t
20. The first word is available the cycle after EF goes HIGH, always.
(if applicable)
WEN2
Q
for the programmable flag offset registers.
t
D
CLK
WEN1
REN1,
WCLK
REN2
0
RCLK
0
–Q
–D
OE
+ t
EF
SKEW1
8
SKEW1
8
(if applicable)
D
LOW
Q
WEN2
WCLK
WEN1
REN1,
t
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
RCLK
> minimum specification, t
REN2
DS
0
0
–D
–Q
OE
EF
t
t
ENS
ENS
8
8
DATAWRITE1
t
ENS
t
DS
(continued)
t
SKEW1
DATA IN OUTPUT REGISTER
t
ENH
t
ENH
D
0 (FIRST
t
FRL
FRL
(maximum) = t
[19]
VALID
t
SKEW1
Write)
t
OLZ
t
FRL
t
REF
CLK
[19]
+ t
SKEW1
t
D
REF
1
. When t
t
OE
t
SKEW1
A
t
REF
< minimum specification, t
t
DS
t
A
D
[20]
2
t
t
ENS
ENS
CY7C4421/4201/4211/4221
DATAWRITE2
t
ENH
t
SKEW1
t
ENH
CY7C4231/4241/4251
D
0
FRL
D
t
A
t
3
FRL
(maximum) = either 2*t
DATA Read
[19]
D
1
D
t
4
REF
Page 10 of 18
CLK
+ t
SKEW1
or