CY7C4281V CYPRESS [Cypress Semiconductor], CY7C4281V Datasheet - Page 13

• Manufacturer Part Number: CY7C4281V
• Description: 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06013 Rev. *A
Switching Waveforms
Notes:
22. If a write is performed on this rising edge of the write clock, there will be Full
23. PAF offset = m.
24. 16K
25. t
Write Programmable Registers
WEN2/LD
Programmable Almost Full Flag Timing
and the rising edge of WCLK is less than t
(if applicable)
SKEW2
WEN1
WCLK
D
0
WEN2
–D
WCLK
REN1,
WEN1
RCLK
m words for CY7C4261V, 32K – m words for CY7C4271V, 64K
REN2
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK
PAF
8
t
CLKH
t
CLKH
(continued)
FULL
t
CLK
t
t
ENS
ENS
t
DS
SKEW2
(M+1)WORDS
IN FIFO
PAE OFFSET
t
t
ENS
ENS
, then PAF may not change state until the next WCLK.
LSB
t
t
ENH
ENH
t
CLKL
t
CLKL
t
ENH
t
DH
Note
PAE OFFSET
Note
m words for CY7C4281V, and 128K
MSB
(m 1) words of the FIFO when PAF goes LOW.
22
23
t
PAF
t
ENS
PAF OFFSET
t
SKEW2
(FULL M) WORDS
LSB
IN FIFO
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
t
ENS
[25]
m words for CY4291V.
t
ENH
[24]
PAF OFFSET
MSB
t
PAF
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