MC14555 MOTOROLA [Motorola, Inc], MC14555 Datasheet - Page 3

• Manufacturer Part Number: MC14555
• Description: PCM Codec-Filter
• Manufacturer: MOTOROLA [Motorola, Inc]

human voice. These devices were developed primarily for
the telephone network to facilitate voice switching and trans-
mission. Once the voice is digitized, it may be switched by
digital switching methods or transmitted long distance (T1,
microwave, satellites, etc.) without degradation. The name
codec is an acronym from “COder” (for the A/D used to digi-
tize voice) and “DECoder” (for the D/A used for reconstruct-
ing voice). A codec is a single device that does both the A/D
and D/A conversions.
ratio of about 30 dB over a dynamic range of about 40 dB.
This can be accomplished with a linear 13–bit A/D and D/A,
but will far exceed the required signal–to–distortion ratio at
amplitudes greater than 40 dB below the peak amplitude.
This excess performance is at the expense of data per sam-
ple. Methods of data reduction are implemented by com-
pressing the 13–bit linear scheme to companded 8–bit
schemes. There are two companding schemes used:
Mu–255 Law specifically in North America, and A–Law
specifically in Europe. These companding schemes are
accepted world wide. These companding schemes follow a
segmented or “piecewise–linear” curve formatted as sign bit,
three chord bits, and four step bits. For a given chord, all six-
teen of the steps have the same voltage weighting. As the
voltage of the analog input increases, the four step bits incre-
ment and carry to the three chord bits which increment.
When the chord bits increment, the step bits double their
voltage weighting. This results in an effective resolution of six
bits (sign + chord + four step bits) across a 42 dB dynamic
range (seven chords above zero, by 6 dB per chord).
Tables 3 and 4 show the linear quantization levels to PCM
words for the two companding schemes.
properly sample a continuous signal, it must be sampled at a
frequency higher than twice the signal’s highest frequency
component. Voice contains spectral energy above 3 kHz, but
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate, a
sample rate of 8 kHz was adopted, consistent with a band-
width of 3 kHz. This sampling requires a low–pass filter to
limit the high frequency energy above 3 kHz from distorting
the in–band signal. The telephone line is also subject to
50/60 Hz power line coupling, which must be attenuated from
the signal by a high–pass filter before the A/D converter.
desired in–band signal, which has spectral images of the in–
band signal modulated about the sample frequency and its
harmonics. These spectral images, called aliasing compo-
nents, need to be attenuated to obtain the desired signal.
The low–pass filter used to attenuate these aliasing compo-
nents is typically called a reconstruction or smoothing filter.
codec, both presampling and reconstruction filters, and a
precision voltage reference on–chip, and require no external
components.
MOTOROLA
A codec–filter is used for digitizing and reconstructing the
To digitize intelligible voice requires a signal–to–distortion
In a sampling environment, Nyquist theory says that to
The D/A process reconstructs a staircase version of the
The MC145554/57/64/67 PCM Codec–Filters have the
DEVICE DESCRIPTION
DIGITAL
FS R
Receive Frame Sync
BCLK R . Following a rising FS R edge, a serial PCM word at
D R is clocked by BCLK R into the receive data register. FS R
also initiates a decode on the previous PCM word. In the ab-
sence of FS X , the length of the FS R pulse is used to deter-
mine whether the I/O conforms to the Short Frame Sync or
Long Frame Sync convention.
D R
Receive Digital Data Input
BCLK R /CLKSEL
Receive Data Clock and Master Clock Frequency
Selector
4.096 MHz, and synchronous with FS R . In synchronous
applications this pin may be held at a constant level; then
BCLK X is used as the data clock for both the transmit and
receive sides, and this pin selects the assumed frequency of
the master clock (see Table 1 in Functional Description).
MCLK R /PDN
Receive Master Clock and Power–Down Control
devices, only one master clock is needed. Whenever FS X is
clocking, MCLK X is used to derive all internal clocks, and the
MCLK R /PDN pin merely serves as a power–down control. If
MCLK R /PDN pin is held low or is clocked (and at least one
of the frame syncs is present), the part is powered up. If this
pin is held high, the part is powered down. If FS X is absent
but FS R is still clocking, the device goes into receive half–
channel mode, and MCLK R (if clocking) generates the
internal clocks.
MCLK X
Transmit Master Clock
it must be 1.536 MHz, 1.544 MHz, or 2.048 MHz.
BCLK X
Transmit Data Clock
4.096 MHz, but it should be synchronous with MCLK X .
D X
Transmit Digital Data Output
PCM data word; otherwise this pin is in a high–impedance
state.
FS X
Transmit Frame Sync
BCLK X . A rising FS X edge initiates the transmission of a
This is an 8 kHz enable that must be synchronous with
If this input is a clock, it must be between 128 kHz and
Because of the shared DAC architecture used on these
This clock is used to derive the internal sequencing clocks;
BCLK X may be any frequency between 128 kHz and
This output is controlled by FS X and BCLK X to output the
This is an 8 kHz enable that must be synchronous with
MC145554 MC145557 MC145564 MC145567
PIN DESCRIPTION
3