CY7C65620-56LTXI CYPRESS [Cypress Semiconductor], CY7C65620-56LTXI Datasheet - Page 4

• Manufacturer Part Number: CY7C65620-56LTXI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Introduction
EZ-USB HX2LP™ is Cypress’s next generation family of
high-performance, low-power USB 2.0 hub controllers. HX2LP is
an ultra low power single chip USB 2.0 hub controller with
integrated upstream and downstream transceivers, a USB serial
interface engine (SIE), USB hub control and repeater logic, and
TT logic. Cypress has also integrated many of the external
passive components, such as pull-up and pull-down resistors,
reducing the overall bill of materials required to implement a hub
design. The HX2LP portfolio consists of:
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This device option is for ultra low-power applications that require
four downstream ports. All four ports share a single transaction
translator. The CY7C65630 is available in 56 QFN and is also
pin-for-pin compatible with the CY7C65640.
■
This device option is for a 2-port bus powered application. Both
ports share a single transaction translator. The CY7C65620 is
available in a 56 QFN.
All device options are supported by Cypress’s world class
reference design kits, which include board schematics, bill of
materials, Gerber files, Orcad files, and thorough design
documentation.
USB Serial Interface Engine
The
CY7C65620/CY7C65630 to communicate with the USB host.
The SIE handles the following USB activities independently of
the Hub Control Block.
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Hub Repeater
The hub repeater manages the connectivity between upstream
and downstream facing ports that are operating at the same
speed. It supports full- or low-speed connectivity and high-speed
connectivity. According to the USB 2.0 specification, the HUB
Repeater provides the following functions:
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Transaction Translator
The TT translates data from one speed to another. A TT takes
high speed split transactions and translates them to full- or
low-speed transactions when the hub is operating at high-speed
(the upstream port is connected to a high-speed host controller)
and has full- or low-speed devices attached. The operating
speed of a device attached on a downstream facing port
determines whether the routing logic connects a port to the TT
or hub repeater. If a full- or low-speed device is connected to the
hub operating at high-speed, the data transfer route includes the
TT. If a high-speed device is connected to this high-speed hub,
Document Number: 38-08037 Rev. *V
CY7C65630: 4-port/single transaction translator
CY7C65620: 2-port/single transaction translator
Bit stuffing and unstuffing
Checksum generation and checking
TOKEN type identification
Address checking.
Sets up and tears down connectivity on packet boundaries
Ensures orderly entry into and out of the suspend state,
including proper handling of remote wakeups.
serial
interface
engine
(SIE)
allows
the
the route only includes the repeater and no TT, because the
device and the hub are operating at the same speed. When the
hub is operating at full-speed (the upstream port is connected to
a full-speed host controller), a high-speed peripheral does not
operate at its full capability. These devices only work at
full-speed. Full- and low-speed devices connected to this hub
operate at their normal speed.
Applications
Typical applications for the HX2LP device family are:
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Functional Overview
The Cypress CY7C65620/CY7C65630 USB 2.0 Hubs are
high-performance, low system cost solutions for USB. The
CY7C65620/CY7C65630 USB 2.0 Hubs integrate 1.5 k
upstream pull-up resistors for full-speed operation and all
downstream 15 k pull-down resistors and series termination
resistors on all upstream and downstream D+ and D– pins. This
results in optimization of system costs by providing built-in
support for the USB 2.0 specification.
System Initialization
On power-up, the CY7C65620/CY7C65630 reads an external
SPI EEPROM for configuration information. At the most basic
level, this EEPROM has the vendor ID (VID), product ID (PID),
and device ID (DID) for the customer’s application. For more
specialized applications, other configuration options can be
specified. See
details.
After reading the EEPROM, if VBUSPOWER (connected to
upstream V
pull-up resistor on D+ to indicate its presence to the upstream
hub, after which a USB bus reset is expected. During this reset,
CY7C65620/CY7C65630 initiates a chirp to indicate that it is a
high-speed peripheral. In a USB 2.0 system, the upstream hub
responds with a chirp sequence, and CY7C65620/CY7C65630
is in a high-speed mode, with the upstream D+ pull-up resistor
turned off. In USB 1.x systems, no such chirp sequence from the
upstream hub is seen, and CY7C65620/CY7C65630 operates
as a normal 1.x hub (operating at full-speed).
Enumeration
After a USB bus reset, CY7C65620/CY7C65630 is in an
unaddressed, unconfigured state (configuration value set to ’0’).
During the enumeration process, the host sets the hub's address
and configuration. After the hub is configured, the full hub
functionality is available.
Standalone hubs
Motherboard hubs
Monitor hubs
Advanced port replicators
Docking stations
Split-PC designs
External personal storage drives
Keyboard hubs
BUS
) is high, CY7C65620/CY7C65630 enables the
Configuration Options on page 13
CY7C65620/CY7C65630
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