CAT9554 CATALYST [Catalyst Semiconductor], CAT9554 Datasheet - Page 9

• Manufacturer Part Number: CAT9554
• Description: 8-bit I2C and SMBus I/O Port with Interrupt
• Manufacturer: CATALYST [Catalyst Semiconductor]

Table 1. Register Command Byte
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data. The SDA line remains stable LOW during the
HIGH period of the acknowledge related clock pulse
(Figure 5).
The CAT9554/9554A respond with an acknowledge
after receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
When the CAT9554/9554A begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT9554/9554A will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition. The master must then issue a STOP
condition to return the CAT9554/9554A to the standby
power mode and place the device in a known state.
Registers and Bus Transactions
The CAT9554/9554A consist of an input port register,
an output port register, a polarity inversion register and
a configuration register. Table 1 shows the register
address table. Tables 2 to 5 list Register 0 through
Register 3 information.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FROM TRANSMITTER
C
o
h (
m
0
0
0
0
FROM RECEIVER
x
x
x
x
e
m
0
0
0
0
) x
DATA OUTPUT
DATA OUTPUT
0
2
3
1
a
n
SCL FROM
d
MASTER
R
R
R
e
e
e
R
a
a
a
P
d
d
d
e
o r
w /
w /
w /
a
d
o t
START
i r
i r
i r
b
e t
e t
e t
c
y
l o
e t
b
b
b
y
y
y
e t
e t
e t
BUS RELEASE DELAY (TRANSMITTER)
P
l o
C
O
r a
o
1
n I
u
f n
y t i
p
p t
g i
t u
t u
F
n i
r u
u
p
v
Figure 8. Acknowledge Timing
p
t a
n
o
e
o
t r
t c
o i
s r
t r
n
o i
e r
o i
e r
n
e r
n
g
g
t s i
e r
g
t s i
t s i
r e
g
r e
t s i
r e
ACK DELAY
r e
9
Table 2. Register 0 – Input Port Register
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine
which register will be written or read.
The input port register is a read only port. It reflects the
incoming logic levels of the I/O pins, regardless of
whether the pin is defined as an input or an output by the
configuration register. Writes to the input port register
are ignored.
Table 3. Register 1 – Output Port Register
Table 4. Register 2 – Polarity Inversion Register
Table 5. Register 3 – Configuration Register
8
d
d
d
d
e
e
e
e
b
b
b
b
a f
a f
a f
a f
t i
t i
t i
t i
u
u
u
u
t l
t l
t l
t l
O
N
C
7 I
0
1
1
1
7
7
7
9
ACK SETUP
O
N
C
6 I
0
1
1
1
6
6
6
O
N
C
5 I
0
1
1
1
5
5
5
BUS RELEASE DELAY (RECEIVER)
O
N
C
4 I
0
1
1
1
4
4
4
CAT9554, CAT9554A
O
N
C
3 I
0
1
1
1
3
3
3
O
N
C
2 I
0
1
1
1
Doc. No. 25088, Rev. B
2
2
2
O
N
C
1 I
0
1
1
1
1
1
1
O
N
C
0 I
0
1
1
1
0
0
0