SY55856UHGTR MICREL [Micrel Semiconductor], SY55856UHGTR Datasheet - Page 2

• Manufacturer Part Number: SY55856UHGTR
• Description: 2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
M9999-011207
[e-mail] or [phone]
/DATA_IN
DATA_IN
/CLK_IN
CLK_IN
PACKAGE/ORDERING INFORMATION
GND
GND
GND
GND
PIN DESCRIPTION
18, 20. 21, 23
Pin Number
25, 26, 31, 32
9, 10, 15, 16
27, 28, 29
2, 4, 5, 7,
32-Pin EPAD-TQFP (H32-1)
17, 19
22, 24
12, 13
6, 8
1
2
3
4
5
6
7
8
1, 3
14
30
11
32 31 30 29 28 27 26 25
9
10 11 12 13 14 15 16
EPAD-TQFP
Top View
H32-1
DELAY_SEL
DATA_OUT,
/DATA_OUT
/CLK_OUT,
/DATA_IN,
S0, S1, S2
Pin Name
CLK_OUT
DATA_IN
CLK_IN,
/CLK_IN
CINV
GND
VCC
LVL
NC
19
18
24
23
22
21
20
17
/DATA_OUT
GND
DATA_OUT
GND
GND
CLK_OUT
GND
/CLK_OUT
Pin Function
CML Input (Differential). This is one of the CML inputs, the data in signal. A delayed
version of this signal appears at DATA_OUT, /DATA_OUT.
Ground.
CML Output (Differential). This is one of the CML outputs, the data output. It is a delayed
version of DATA_IN , /DATA_IN.
CML Input (Differential). This is one of the differential CML inputs, the clock in signal. A
delayed version of this input appears at CLK_OUT, /CLK_OUT.
CML Output (Differential). This is one of the CML outputs, the clock output. It is a delayed,
copy of CLK_IN, /CLK_IN.
Power Supply.
VT Input (Single Ended). This is the clock inversion select signal. This input optionally
inverts the CLK_IN, /CLK_IN signal which results in an inverted CLK_OUT, /CLK_OUT. A
voltage below the VT threshold results in no inversion. A voltage above the threshold value
results in an inversion from the clock input to the clock output. Refer to the “VT input”
section below.
Analog Input. This input determines what level differentiates logic high from logic low. This
input affects the behavior of the CINV, S0, S1 and S2 inputs. Please refer to the “VT input“
section below for more details. For the control interface, see Figure 3a. For TTL control
interface, see Figure 3b.
VT Input (Single Ended). CML compatible control logic. This is the delay path control input.
Logic high delays the clock signal with respect to the data signal. A logic low delays the
data signal with respect to the clock signal. Inputs S2, S1 and S0 control amount of delay.
input. These three bits define how much relative delay will occur between the data and
clock signals, as per the truth table shown in Table 2. For the control logic interface, see
Figure 3a. For TTL control interface, see Figure 3b. S0=LSB.
No Connect.
VT Input (Single Ended). CML compatible control logic. This is the delay selection control
Ordering Information
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
Part Number
SY55856UHI
SY55856UHITR
SY55856UHG
SY55856UHGTR
(3)
(2)
(2, 3)
2
Package
H32-1
H32-1
H32-1
H32-1
Type
(1)
Operating
Industrial
Industrial
Industrial
Industrial
Range
Pb-Free bar line indicator Pb-Free
Pb-Free bar line indicator Pb-Free
A
55856U with
55856U with
= 25 C, DC Electricals only.
Package
Marking
55856U
55856U
SuperLite™
SY55856U
NiPdAu
NiPdAu
Finish
Sn-Pb
Sn-Pb
Lead