AD8310ARMZ-REEL71 AD [Analog Devices], AD8310ARMZ-REEL71 Datasheet - Page 12

• Manufacturer Part Number: AD8310ARMZ-REEL71
• Description: Fast, Voltage-Out DC-440 MHz, 95 dB Logarithmic Amplifier
• Manufacturer: AD [Analog Devices]

AD8310
Occasionally, it might be desirable to use the dc-coupled
potential of the AD8310 in baseband applications. The main
challenge here is to present the signal at the elevated common-
mode input level, which might require the use of low noise, low
offset buffer amplifiers. In some cases, it might be possible to
use dual supplies of ±3 V, which allow the input pins to operate
at ground potential. The output, which is internally referenced
to the COMM pin (now at −3 V), can be positioned back to
ground level, with essentially no sensitivity to the particular
value of the negative supply.
OFFSET INTERFACE
The input-referred dc offsets in the signal path are nulled via
the interface associated with Pin 3, shown in Figure 25. Q1 and
Q2 are the first-stage input transistors, having slightly unbal-
anced load resistors, resulting in a deliberate offset voltage of
about 1.5 mV referred to the input pins. Q3 generates a small
current to null this error, dependent on the voltage at the OFLT
pin. When Q1 and Q2 are perfectly matched, this voltage is
about 1.75 V. In practice, it can range from approximately 1 V to
2.5 V for an input-referred offset of ±1.5 mV.
INLO
INHI
1
8
C
C
C
M
P
D
COM
COM
4kΩ
DETECTORS
2kΩ
FROM ALL
Figure 24. Signal Input Interface
COMM
VPOS
TYP 2.2V FOR
3V SUPPLY,
3.2V AT 5V
DETECTORS
TOP-END
LGP
LGN
5
2
BIAS
60µA
COMM
2
0.4pF
S
S
6kΩ
6kΩ
~3kΩ
1.25kΩ
1.25kΩ
Q1
125Ω
Q2
I
2.4mA
1.25kΩ
1.25kΩ
E
Figure 26. Simplified Output Interface
5
VPOS
2µA/dB
R1
3kΩ
0.4pF
Rev. D | Page 12 of 24
6
BFIN
4kΩ
STAGE
In normal operation using an ac-coupled input signal, the OFLT
pin should be left unconnected. The g
when the chip is disabled, converts a residual offset (sensed at a
point near the end of the cascade of amplifiers) to a current.
This is integrated by the on-chip capacitor, C
external capacitance, C
applied back to the input stage in the polarity needed to null the
output offset. From a small-signal perspective, this feedback
alters the response of the amplifier, which exhibits a zero in its
ac transfer function, resulting in a closed-loop high-pass −3 dB
corner at about 2 MHz. An external capacitor lowers the high-
pass corner to arbitrarily low frequencies; using 1 µF, the 3 dB
corner is at 60 Hz.
OUTPUT INTERFACE
The nine detectors generate differential currents, having an
average value that is dependent on the signal input level, plus a
fluctuation at twice the input frequency. These are summed at
nodes LGP and LGN in Figure 26. Further currents are added at
these nodes to position the intercept by slightly raising the
output for zero input and to provide temperature compensation.
INPUT
BIAS,
4kΩ
1.2V
Q1
125Ω
Figure 25. Offset Interface and Offset-Nulling Path
Q2
Q3
BIAS
BALANCE
36kΩ
16µA AT
0.2pF
OFLT
, to generate the voltage that is
Q4
48kΩ
MAIN GAIN
STAGES
1kΩ
3kΩ
OFLT
3
m
C
cell, which is gated off
S
OFLT
VOUT
4
HP
g
, plus any added
m
33pF
AVERAGE
ERROR
CURRENT
5
2
TO LAST
DETECTOR
VPOS
COMM