PCA84C441 PHILIPS [NXP Semiconductors], PCA84C441 Datasheet - Page 12

• Manufacturer Part Number: PCA84C441
• Description: 8-bit microcontrollers with OSD and VST
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9
9.1
The PCA84C640 has one 14-bit PWM DAC output (TDAC)
with a resolution of 16384 levels for Voltage Synthesized
Tuning. The PWM DAC (see Fig.10) consists of:
The polarity of output TDAC is selected with bit P14LVL.
Setting the bit P14LVL to:
9.1.1
The counter is continuously running and is clocked by f
The period of the clock,
The repetition time for one complete cycle of the counter:
The repetition time for one cycle of the lower 7-bits of the
counter is:
Therefore, the number of t
cycle t
9.1.2
In order to ensure correct operation, interface data latch
VSTH is loaded first and then interface data latch VSTL.
The contents of:
At the beginning of the first t
of VSTL, both data latches are loaded into data latch
VSTREG. After the contents of VSTH and VSTL are
latched into VSTREG, one t
generate the appropriate pulse pattern.
To ensure correct DAC conversion, two (2) t
should be allowed before beginning the next sequence.
1996 Nov 29
N
t
t
sub
r
14-bit counter
Two 7-bit DAC interface data latches (VSTH and VSTL)
One 14-bit DAC data latch (VSTREG)
Pulse control.
Logic 1, sets the TDAC output to the default polarity
Logic 0, inverts the TDAC output.
VSTH are used for coarse adjustment
VSTL are used for fine adjustment.
8-bit microcontrollers with OSD and VST
=
=
VST CONTROL
t
---------------------------
=
t
0
r
0
t
14-bit PWM DAC
is:
0
t
0
14-
D
16 384
16 384
ATA AND INTERFACE LATCHES
128
128
BIT COUNTER
=
128
t
0
sub
sub
=
sub
------------- -
f
periods in a complete
XTAL
period following the loading
period is needed to
3
sub
periods
0
.
12
9.2
The coarse adjustment output (OUT1) is reset to LOW
(inactive) at the start of each t
It will remain LOW until the time
elapsed and then will go HIGH and remain so until the next
t
9.3
Fine adjustment is achieved by generating additional
pulses at the start of particular sub-periods (t
These additional pulses have a width of t
The sub-period in which a pulse is added is determined by
the contents of VSTL interface latch.
Table 3 gives the numbers of the t
an additional pulse is generated, depending on the bit in
VSTL being a logic 0. When more than one bit is a logic 0
a combination of additional pulses are generated.
For example, if VSTL = 1111010, which is a combination
of
then additional pulses will be given in sub-periods
16, 48, 64, 80 and 112; this is illustrated in Fig.12.
If VSTH = 0011101, VSTL = 1111010 and P14LVL = 0,
then the TDAC output is as shown in Fig.13.
Table 3 Additional pulse distribution
sub
VSTL = 1111110: sub-period 64, and
VSTL = 1111011: sub-periods 16, 48, 80 and 112,
LOWER
1111101
1111011
1011111
1111110
1110111
1101111
0111111
period starts.
(VSTL)
7 BITS
Coarse adjustment
Fine adjustment
84C44X; 84C64X; 84C84X
64
32, 96
16, 48, 80, 112
8, 24, 40, 56, 72, 88, 104, 120
4, 12, 20, 28, 36, 44, 52, 60 .... 116, 124
2, 6, 10, 14, 18, 22, 26, 30, .... 122, 126
1, 3, 5, 7, 9, 11, 13, 15, 17, .... 125, 127
ADDITIONAL PULSE IN
SUB-PERIODS t
sub
period.
subn
t
0
Product specification
, at the start of which
VSTH
0
.
subn
subn
+
1
).
has