M41ST84WMH1 STMICROELECTRONICS [STMicroelectronics], M41ST84WMH1 Datasheet - Page 13

• Manufacturer Part Number: M41ST84WMH1
• Description: 5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 14. Alternate READ Mode Sequence
WRITE Mode
In this mode the master transmitter transmits to
the M41ST84Y/W slave receiver. Bus protocol is
shown in Figure 15, page 13. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
Figure 15. WRITE Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
S
ADDRESS
SLAVE
S
ADDRESS
SLAVE
ADDRESS (An)
WORD
DATA n
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST84Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
12, page 12) and again after it has received the
word address and each data byte.
DATA n
DATA n+1
DATA n+1
M41ST84Y, M41ST84W
DATA n+X
DATA n+X
AI00895
AI00591
P
P
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