M41T00AUD_12 STMICROELECTRONICS [STMicroelectronics], M41T00AUD_12 Datasheet - Page 11

• Manufacturer Part Number: M41T00AUD_12
• Description: Serial real-time clock (RTC) with audio
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M41T00AUD
4.1
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
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Accordingly, the following bus conditions have been defined:
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Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called "transmitter", the receiving device
that gets the message is called "receiver". The device that controls the message is called
"master". The devices that are controlled by the master are called "slaves".
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A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as control
signals.
Bus not busy. Both data and clock lines remain high.
Start data transfer. A change in the state of the data line, from high to low, while the
clock is high, defines the START condition.
Stop data transfer. A change in the state of the data line, from low to high, while the
clock is high, defines the STOP condition.
Data valid. The state of the data line represents valid data when after a start condition,
the data line is stable for the duration of the high period of the clock signal. The data on
the line may be changed during the low period of the clock signal. There is one clock
pulse per bit of data.
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This
acknowledge bit is a low level put on the bus by the receiver, whereas the master
generates an extra acknowledge related clock pulse.
Doc ID 13480 Rev 5
Operation
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