M41T00M STMICROELECTRONICS [STMicroelectronics], M41T00M Datasheet - Page 7

• Manufacturer Part Number: M41T00M
• Description: Serial Access TIMEKEEPER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 10. AC Characteristics
(T
Note: 1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
WRITE MODE
In this mode the master transmitter transmits to
the M41T00 slave receiver. Bus protocol is shown
in Figure 10. Following the START condition and
slave address, a logic ’0’ (R/W = 0) is placed on the
bus and indicates to the addressed device that
word address An will follow and is to be written to
the on-chip address pointer. The data word to be
written to the memory is strobed in next and the in-
ternal address pointer is incremented to the next
memory location within the RAM on the reception
of an acknowledge clock. The M41T00 slave re-
ceiver will send an acknowledge clock to the mas-
ter transmitter after it has received the slave
address and again after it has received the word
address and each data byte (see Figure 9).
READ MODE
In this mode, the master reads the M41T00 slave
after setting the slave address (see Figure 11).
Following the write mode control bit (R/W = 0) and
the acknowledge bit, the word address An is writ-
t
A
HD:DAT
Symbol
t
t
t
t
SU:STO
HD:STA
SU:STA
SU:DAT
t
= –40 to 85°C; V
t
t
f
HIGH
LOW
SCL
BUF
t
t
R
F
(1)
SCL Clock Frequency
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
START Condition Hold Time
(after this period the first clock pulse is generated)
START Condition Setup Time
(only relevant for a repeated start condition)
Data Setup Time
Data Hold Time
STOP Condition Setup Time
Time the bus must be free before a new transmission can start
CC
= 2.0V to 5.5V)
Parameter
ten to the on-chip address pointer. Next the
START condition and slave address are repeated,
followed by the READ mode control bit (R/W = 1).
At this point, the master transmitter becomes the
master receiver. The data byte which was ad-
dressed will be transmitted and the master receiv-
er will send an acknowledge bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an acknowledge bit. The
M41T00 slave transmitter will now place the data
byte at address A
ceiver reads and acknowledges the new byte and
the address pointer is incremented to A
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
An alternate READ mode may also be implement-
ed, whereby the master reads the M41T00 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer, see Figure12.
n+1
Min
250
4.7
4.7
4.7
4.7
0
4
4
0
on the bus. The master re-
Max
100
300
1
n+2
M41T00
.
Unit
kHz
µs
µs
µs
ns
µs
µs
ns
µs
µs
µs
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