M48T02-150PC1TR STMICROELECTRONICS [STMicroelectronics], M48T02-150PC1TR Datasheet - Page 6

• Manufacturer Part Number: M48T02-150PC1TR
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M48T02, M48T12
Table 5. DC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
OPERATION MODES
As Figure 4, page 4 shows, the static memory ar-
ray and the quartz controlled clock oscillator of the
M48T02/12 are integrated on one silicon chip. The
two circuits are interconnected at the upper eight
memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 7F8h-7FFh. The clock locations con-
tain the year, month, date, day, hour, minute, and
second in 24 hour BCD format. Corrections for 28,
29 (leap year - valid until 2100), 30, and 31 day
months are made automatically.
Byte 7F8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
Table 6. Operating Modes
Note: X = V
6/19
Deselect
WRITE
READ
READ
Deselect
Deselect
Symbol
I
I
Mode
I
CC1
CC2
V
LO
V
V
V
I
I
IL
CC
2. Outputs deselected.
3. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.'
4. Negative spikes of –1V allowed for up to 10ns once per Cycle.
1. See Table 10, page 11 for details.
OH
LI
OL
IH
(2)
(4)
(3)
(3)
IH
or V
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
SO
IL
; V
4.75 to 5.5V
4.5 to 5.5V
to V
SO
V
V
= Battery Back-up Switchover Voltage.
PFD
or
SO
CC
(1)
(min)
Parameter
(1)
V
V
V
V
E
X
X
IH
IL
IL
IL
A
= 0 to 70°C; V
V
V
G
X
X
X
X
IH
IL
Test Condition
0V
0V
E = V
Outputs open
I
I
CC
OL
OH
E = V
V
consisting of BiPORT™ READ/WRITE memory
cells. The M48T02/12 includes a clock control cir-
cuit which updates the clock bytes with current in-
formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion. When V
protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
operation brought on by low V
low approximately 3V, the control circuitry con-
nects the battery which maintains data and clock
operation until valid power returns.
= 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
V
= 2.1mA
CC
= –1mA
OUT
IN
V
V
– 0.2V
V
W
X
X
X
IH
IH
IH
IL
V
V
CC
CC
(1)
DQ0-DQ7
CC
High Z
High Z
High Z
High Z
D
D
OUT
is out of tolerance, the circuit write
IN
–0.3
Min
2.2
2.4
Battery Back-up Mode
CMOS Standby
V
CC
CC
Max
0.8
0.4
Standby
±1
±1
80
. As V
3
3
Power
Active
Active
Active
+ 0.3
CC
falls be-
Unit
mA
mA
mA
µA
µA
V
V
V
V