M48T201V-70MH1 STMICROELECTRONICS [STMicroelectronics], M48T201V-70MH1 Datasheet - Page 8

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M48T201V-70MH1

Manufacturer Part Number
M48T201V-70MH1
Description
3.3V-5V TIMEKEEPER CONTROLLER
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
M48T201Y, M48T201V
READ Mode
The M48T201Y/V executes a READ Cycle when-
ever W (WRITE Enable) is high and E (Chip En-
able) is low. The unique address specified by the
address inputs (A0-A18) defines which one of the
on-chip TIMEKEEPER
SRAM locations is to be accessed. When the ad-
dress presented to the M48T201Y/V is in the
range of 7FFFFh-7FFF0h, one of the on-board
TIMEKEEPER registers is accessed and valid
data will be available to the eight data output driv-
ers within t
stable, providing that the E and G access times
are also satisfied. If they are not, then data access
Figure 5. G
8/33
ADDRESS
G
G CON
E
AVQV
CON
Timing When Switching Between RTC and External SRAM
after the address input signal is
7FFF0h - 7FFFFh
®
RTC
registers or external
External SRAM
00000h - 7FFEFh
tAOEL
must be measured from the latter occurring signal
(E or G) and the limiting parameter is either t
for E or t
time. When one of the on-chip TIMEKEEPER reg-
isters is selected for READ, the G
remain inactive throughout the READ Cycle.
When the address value presented to the
M48T201Y/V is outside the range of TIMEKEEP-
ER registers, an external SRAM location will be
selected. In this case the G signal will be passed
to the G
t
AOEL
7FFF0h - 7FFFFh
tAOEH
RTC
or t
GLQV
CON
OERL
tOERL
pin, with the specified delay times of
for G rather than the address access
.
00000h - 7FFEFh
External SRAM
AI02333
CON
tRO
signal will
ELQV

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