74LVC374A PHILIPS [NXP Semiconductors], 74LVC374A Datasheet - Page 2

• Manufacturer Part Number: 74LVC374A
• Description: Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State
• Manufacturer: PHILIPS [NXP Semiconductors]

1. C
2. The condition is V
FEATURES
DESCRIPTION
The 74LVC374A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
QUICK REFERENCE DATA
GND = 0V; T
NOTE:
ORDERING INFORMATION
Philips Semiconductors
t
f
C
C
20-Pin Plastic Shrink Small Outline (SO)
20-Pin Plastic Shrink Small Outline (SSOP) Type II
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
1998 Jul 29
PHL
max
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 2.7V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
High impedance when V
8-bit positive edge-triggered register
Independent register and 3-State buffer operation
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
I
PD
P
f
f
S (C
i
o
PD
D
= input frequency in MHz; C
/t
= output frequency in MHz; V
PLH
= C
SYMBOL
L
is used to determine the dynamic power dissipation (P
x V
PD
amb
CC
x V
2
=25 C; t
CC
x f
2
o
) = sum of outputs.
x f
I
= GND to V
i
PACKAGES
+ S (C
r
Propagation delay
CP to Q
maximum clock frequency
Input capacitance
Power dissipation capacitance per
flip-flop
= t
CC
f
= 0V
v 2.5ns
L
x V
L
CC
n
= output load capacity in pF;
CC
CC
= supply voltage in V;
2
PARAMETER
x f
o
) where:
TEMPERATURE
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
D
in mW):
RANGE
C
V
Notes 1 and 2
CC
L
2
= 50pF
= 3.3V
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC374A is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops.
that meet the setup and hold times requirements on the
LOW-to-HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The ’374’ is functionally identical to the ’574’, but the ’574’ has a
different pin arrangement.
The eight flip-flops will store the state of their individual D-inputs
CONDITIONS
NORTH AMERICA
74LVC374A PW
74LVC374A DB
74LVC374A D
OUTSIDE
NORTH AMERICA
7LVC374APW DH
74LVC374A DB
74LVC374A D
TYPICAL
150
4.8
5.0
20
74LVC374A
Product specification
853-1861 19802
PKG. DWG. #
SOT163-1
SOT339-1
SOT360-1
UNIT
MHz
pF
pF
ns