74LVC823A PHILIPS [NXP Semiconductors], 74LVC823A Datasheet - Page 2

• Manufacturer Part Number: 74LVC823A
• Description: 9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State
• Manufacturer: PHILIPS [NXP Semiconductors]

1. C
2. The condition is V
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
NOTES:
ORDERING INFORMATION
Philips Semiconductors
24-Pin Plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
1998 Sep 24
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 2.7V to 3.6V
Complies with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5V
CMOS low power consumption
Direct interface with TTL levels
9-bit positive edge-triggered register
Independent register and 3-State buffer operation
Flow-through pin-out architecture
9-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
P
f
f
i
o
PD
D
= input frequency in MHz; C
= output frequency in MHz; V
(C
= C
SYMBOL
t
t
is used to determine the dynamic power dissipation (P
L
PHL
f
C
PD
max
C
V
PD
/t
/t
I
CC
amb
PLH
V
2
PACKAGES
CC
= 25 C; t
f
2
o
) = sum of the outputs.
I
= GND to V
f
i
) (C
Propagation delay
CP to Q
Propagation delay
MR to Q
Maximum clock frequency
Input capacitance
Power dissipation capacitance per
flip-flop
r
= t
f
L
L
2.5 ns
n
CC
n
= output load capacity in pF;
CC
V
CC
= supply voltage in V;
PARAMETER
2
f
o
) where:
TEMPERATURE RANGE
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
D
in W)
C
V
C
V
Notes 1 and 2
L
L
CC
L
CC
2
= 50 pF;
= 50 pF;
= 3.3 V
= 3.3 V
DESCRIPTION
The 74LVC823A is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-state
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC823A is a 9-bit D-type flip-flop with common clock (CP),
Clock Enable (CE), Master Reset (MR) and 3-State outputs for
bus-oriented applications.
The nine flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition provided CE is LOW. When CE is HIGH the flip-flops
hold their data.
A LOW on MR resets all flip-flops.
When OE is LOW, the contents of the nine flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
CONDITIONS
ORDERING CODE
74LVC823A PW
74LVC823A DB
74LVC823A D
TYPICAL
150
5.1
5.2
5.0
27
74LVC823A
Product specification
PKG. DWG. #
SOT137-1
SOT340-1
SOT355-1
853-2124 20078
UNIT
MHz
pF
pF
ns
ns