AD7366-5ARUZ AD [Analog Devices], AD7366-5ARUZ Datasheet - Page 9

• Manufacturer Part Number: AD7366-5ARUZ
• Description: True Bipolar Input, Dual 1us, 12-Bit, 2-Channel SAR ADC
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
9,16
10
11,12
13,14
15
18
19
20
21
22
24
D
V
V
V
V
REFSEL
CS
SCLK
CONVST
BUSY
DGND
CAP
SS
A1
B2
DD
, V
, V
A,D
B1
A2
CAP
B
be placed on the AV
Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference
buffer for each respective ADC. For best performance it is recommended to use 680nF decoupling capacitor
on these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and
applied externally to the rest of a system.
Negative power supply voltage. This is the negative supply voltage for the Analog Input section. The supply
must be less than a maximum voltage of -11.5V for all input ranges. See Table 6 for further details. 10 µF
and 100 nF decoupling capacitors should be placed on the V
Analog Inputs of ADC A. These are both single-ended analog inputs. The Analog input range on these
channels is determined by the RANGE0 and RANGE1 pins.
Analog Inputs of ADC B. These are both single-ended analog inputs. The Analog input range on these
channels is determined by the RANGE0 and RANGE1 pins.
Positive power supply voltage. This is the positive supply voltage for the Analog Input section. The supply
must be greater than a minimum voltage of 11.5V for all the analog input ranges. See Table 6 for further
details. 10 µF and 100 nF decoupling capacitors should be placed on the V
Internal/External Reference Selection. Logic input. If this pin is tied to a logic high, the on-chip 2.5 V
reference is used as the reference source for both ADC A and ADC B. In addition, Pin D
must be tied to decoupling capacitors. If the REF SELECT pin is tied to GND, an external reference can be
supplied to the AD7366 through the D
Chip Select. Active low logic input. This input frames the serial data transfer. When CS is logic low the
output bus is enabled and the conversion result is output on D
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7366.
Conversion Start. Edge triggered logic input. On the falling edge of this input the track/hold goes into hold
mode and conversion is initiated. If CONVST is low at the end of a conversion, the part goes into power-
down mode. In this case, the rising edge of CONVST will instruct the part to power up again.
BUSY Output. Transitions high when a conversion is started and remains high until the conversion is
complete.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7366. The DGND pin
should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the
same potential and must not be more than 0.3 V apart, even on a transient basis.
CC
pins.
Rev. PrG | Page 9 of 17
CAP
A and/or D
CAP
B pins.
SS
OUT
pin.
A, and D
DD
OUT
pin.
B.
CAP
A and Pin D
AD7366
CAP
B