LM9810 NSC [National Semiconductor], LM9810 Datasheet
LM9810
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LM9810 Summary of contents
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... CIS and CCD sensors. The LM9810 has a 10 bit 6MHz ADC, and the LM9820 has a 12 bit 6MHz ADC. The LM9810 and LM9820 are pin-for-pin and func- tionally compatible. ...
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Block Diagram Sampler Mux REF+ or Select V V REF- signal V reference SampCLK NewLine MCLK SampCLK ADC Clock PGA V SIG x3 Boost .93 ...
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Absolute Maximum Ratings + Positive Supply Voltage ( With Respect to GND= = AGND DGND Voltage On Any Input or Output Pin Input Current at any pin (Note 3) Package Input Current (Note 3) Package ...
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... LM9810 Electrical Characteristics The following specifications apply for = AGND all other limits T =T =25°C. All LSB limits are in units of the LM9810’s 10 bit ADC. (Notes 7, 8, & 12 MIN MAX A J Symbol Parameter ADC Characteristics Resolution with No Missing Codes ...
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LM9820 Electrical Characteristics The following specifications apply for = AGND all other limits T =T =25°C. All LSB limits are in units of the LM9820’s 12 bit ADC. (Notes 7, 8, & 12) A ...
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AC Electrical Characteristics The following specifications apply for AGND limits apply for all other limits MIN MAX Symbol Parameter f Maximum Frequency MCLK MCLK Duty Cycle MCLK t period MCLK MCLK ...
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... The calculated digital switching current VD will be drawn through the pin and should be considered as part of the total power budget for he LM9810/20. VA and as shown below. This input protection, in combination with the external clamp capacitor and the output ...
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... ADC. When is high, D[5-0] enter TRI- NewLine STATE and , and interface for programming the configuration registers. VD with a AGND DGND - D5 D0 AGND LM9810 Output Mode ( Low) NewLine through a .05uF Nominally D2 D1 controls the con- D0 LM9820 is low and Output Mode . When SampCLK ( ...
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Timing Diagrams Diagram 1: Pixel Conversion Timing and Latency Diagram 2: Diagram 3: Timing for Programming the Configuration Registers and Output Data Timing ( SampCLK NewLine 9 low) http://www.national.com ...
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Timing Diagrams NewLine RS O ptic al B lack P ixel OS Clamp Signal (Internal) Clamp On SampCLK Ø1 (Even/Odd Mode) Ø2 (Even/Odd Mode) Ø1 (Standard Mode) Ø2 (Standard Mode) CCD Reset signal OS SampCLK O ptica l B lack ...
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Table 1: Configuration Register Address Table Address Address (Decimal) (Binary Data Bits B5 ...
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Table 2: Configuration Register Parameters Parameter (Address) B5 CDS Enable 0 ( Signal Polarity 0 ( Color Mode ( ...
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... Control Bits Positive Offset Negative Offset LM9810: Offset = 5LSBs * Offset Value * PGA Gain B2 B1 B0(LSB) LM9820: Offset = 20LSBs * Offset Value * PGA Gain (LSB) LM9810 LSBs ...
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Table 2: Configuration Register Parameters Parameter (Address) Production Test and Power Down (7) Production Test B4 B5 (7) Power Down B0 Enable 0 (7) 1 (Continued) Control Bits Should all be set to zero for normal operation ...
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... OS (CIS) OS (CCD) OS SampCLK When the LM9810/ CIS mode (Register 0, B5=1), it uses either REF+ REF- of the Sampling and Color Mode register) as the reference (or black) voltage for each pixel ...
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... ADC output code greater than zero for all the pixels when scanning a black line. With a PGA gain of 1V/V, each LSB of the offset DAC typically adds the equivalent of 5 LM9810 LSBs or 20 LM9820 LSBs, providing a total offset adjustment range of ±150 LM9810 LSBs or ±590 LM9820 LSBs. The Offset DAC’s ...
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... LM9810/20 leakage current should be no more than 20nA. With C PGA CDS disabled, which will likely be the case when CIS sensors are used, the LM9810/20 leakage current can be as high as 25uA at the maximum conversion rate. 2.1.1 CDS mode Minimum Clamp Capacitor Calculation: The following equation takes the maximum leakage current into ...
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... On subsequent lines, the only error will is low. If the applied be the droop across a single line which should be significantly less than the initial error. If the LM9810/20 is operating in CDS mode and multiple lines are used to charge up the clamping capacitors after power-up, then a clamp capacitor value of 0.01µ ...
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... Figure 6: LM9810/20 Relative Event Timing The LM9810/ densely designed, mixed-signal, monolithic semiconductor. In creating the timing for the LM9810/20, it must be considered that internal events, such as ADC sampling, and output data bus switching can potentially affect coincident events such as input signal sampling or offset DAC settling. One event ...
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Physical Dimensions inches (millimeters) 20 pin (.300” Wide) Molded Small Outline Package 20 http://www.national.com ...
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LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems ...