AD9287BCPZRL-100 AD [Analog Devices], AD9287BCPZRL-100 Datasheet - Page 31

• Manufacturer Part Number: AD9287BCPZRL-100
• Description: Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: AD [Analog Devices]

Table 15. Memory Map Register
Addr.
(Hex)
Chip Configuration Registers
00
01
02
Device Index and Transfer Registers
05
FF
ADC Functions
08
09
0D
Parameter Name
chip_port_config
chip_id
chip_grade
device_index_A
device_update
modes
clock
test_io
Bit 7
(MSB)
0
X
X
X
X
X
User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Bit 6
LSB first
1 = on
0 = off
(default)
Child ID 6:4
(identify device variants of Chip ID)
011 = 100 MSPS
X
X
X
X
Bit 5
Soft
reset
1 = on
0 = off
(default)
Clock
Channel
DCO
1 = on
0 = off
(default)
X
X
X
Reset
PN long
gen
1 = on
0 = off
(default)
(AD9287 = 0x05), (default)
8-bit Chip ID Bits 7:0
Bit 4
1
Clock
Channel
FCO
1 = on
0 = off
(default)
X
X
X
Reset
PN short
gen
1 = on
0 = off
(default)
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X
Bit 3
1
X
Data
Channel
D
1 = on
(default)
0 = off
X
X
Output test mode—see
Digital Outputs and Timing
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checker board output
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = user input
1001 = one/zero bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
Bit 2
Soft
reset
1 = on
0 = off
(default)
X
Data
Channel
C
1 = on
(default)
0 = off
X
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
X
Bit 1
LSB first
1 = on
0 = off
(default)
X
Data
Channel
B
1 = on
(default)
0 = off
X
X
Table 9
section
in the
Bit 0
(LSB)
0
X
Data
Channel
A
1 = on
(default)
0 = off
transfer
1 = on
0 = off
(default)
Duty
cycle
stabilizer
1 = on
(default)
0 = off
SW
Default
Value
(Hex)
0x18
0x05
Read
only
0x0F
0x00
0x00
0x01
0x00
Default Notes/
Comments
The nibbles
should be
mirrored so that
LSB- or MSB-first
mode registers
correctly
regardless of
shift mode.
Default is unique
chip ID, different
for each device.
This is a read-
only register.
Child ID used to
differentiate
graded devices.
Bits are set to
determine which
on-chip device
receives the next
write command.
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
various generic
modes of chip
operation.
Turns the
internal duty
cycle stabilizer
on and off.
When set, the
test data is
placed on the
output pins in
place of normal
data.
AD9287