AD5755-1x AD [Analog Devices], AD5755-1x Datasheet
AD5755-1x
Related parts for AD5755-1x
AD5755-1x Summary of contents
Page 1
... Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity GENERAL DESCRIPTION The AD5755 quad, voltage and current output DAC, which operates with a power supply range from -26v to +33v. On chip dynamic power control minimizes package power dissipation in current mode. This is achieved by regulating the voltage on the output driver from between 7V-30V ...
Page 2
... AC Performance Characteristics ................................................ 7 Timing Characteristics ................................................................ 8 Absolute Maximum Ratings .......................................................... 11 ESD Caution ................................................................................ 11 Pin Configuration and Function Descriptions ........................... 12 Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 16 DAC Architecture ....................................................................... 16 Power On State of AD5755-1 .................................................... 16 Serial Interface ............................................................................ 17 Transfer Function ....................................................................... 17 Registers ........................................................................................... 18 Programming Sequence to Write/Enable the Output Correctly ...................................................................................... 19 Changing and Reprogramming the Range ............................. 19 Data Registers ............................................................................. 20 Control Registers ...
Page 3
... TBD nF 2 µF Rev. PrD | Page AD5755 unless otherwise noted. MIN MAX Test Conditions/Comments AVDD needs to have min TBDv headroom on output. AVDD/AVSS need to have min TBDv headroom on output. AVDD needs to have min TBDv headroom on output. AVDD/AVSS need to have min TBDv headroom on output ...
Page 4
... AD5755-1 Parameter 1 DC Output Impedance DC PSRR CURRENT OUTPUT Output Current Ranges Resolution ACCURACY (External R ) Set Total Unadjusted Error (TUE) TUE TC 2 Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift 2 Gain Error 2 Gain TC Full-Scale Error 2 Full-Scale TC ACCURACY (Internal R ) Set ...
Page 5
... V −0.5 −1 +1 µ Rev. PrD | Page AD5755-1 Test Conditions/Comments Chosen such that compliance is not exceeded. Plus see graph on load vs AVcc and DCDC switching freq. Will need appropriate cap at higher inductance values. See Page X of Datasheet. For specified performance T = 25°C ...
Page 6
... AD5755-1 Parameter 1 FAULT V , Output Low Voltage Output Low Voltage Output High Voltage OH POWER REQUIREMENTS DVDD, AVCC Input Voltage AIcc Power Dissipation 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Guaranteed by design and characterization; not production tested. ...
Page 7
... LSB p-p 80 µV rms TBD nV/√Hz TBD uA/µs TBD µs Rev. PrD | Page AD5755 unless otherwise noted. MIN MAX Test Conditions/Comments 10 V step to ±0.03% FSR 100mv step to 1 LSB (16-Bit LSB) (16-Bit LSB) Measured at 10 kHz 100mV 150KHz Sinewave superimposed on ...
Page 8
... AD5755-1 TIMING CHARACTERISTICS AVDD = 15V, AVSS = -15V/0V, V BOOSTA,B,C,D GNDSW = 0 V, REFIN= +5, V A,B,C,D OUT Table 4. Parameter Limit 198 500 11 t See AC Performance 12 Characteristics TBD ...
Page 9
... SDIN MSB LDAC V OUT LDAC = 0 V OUT CLEAR V OUT ALERT RESET FAULT LSB Figure 2. Serial Interface Timing Diagram Rev. PrD | Page AD5755-1 ...
Page 10
... AD5755-1 SCLK 1 SYNC MSB SDIN INPUT WORD SPECIFIES REGISTER TO BE READ MSB SDO UNDEFINED SCLK SYNC DUT_ DUT_ X SDIN R/W X AD1 AD0 SDO DISABLED SDO LSB MSB LSB MSB Figure 3. Readback Timing Diagram X DB15 DB14 SDO Status Status ...
Page 11
... −0 AVDD + 0 (whichever is less) −0.3 to +33 V −0 −0 +0.3 V −40°C to +105°C −65°C to +150°C 125°C 20°C/W (T max – T )/θ JEDEC Industry Standard J-STD-020 Rev. PrD | Page AD5755-1 ...
Page 12
... AD5755-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 RSETB PIN 1 INDICATOR RSETA 2 REFGND 3 REFGND 4 5 AD0 6 AD1 7 SYNC SCLK 8 SDIN 9 10 SDO 11 DVDD DGND 12 13 LDAC 14 15 ALERT FAULT 16 Table 6. Pin Function Descriptions Pin No. Mnemonic Description An external, precision, low drift 15 k Ω current setting resistor can be connected to this pin to improve the ...
Page 13
... It should be noted that OUT_B for correct operation. Rev. PrD | Page ‘s output buffer. Connecting a 220 pF capacitor OUT_A . This pin must stay within ±3.0 OUT_A ‘s output buffer. Connecting a 220 pF capacitor OUT_B . This pin must stay within ±3.0 OUT_B AD5755-1 ...
Page 14
... AD5755-1 Pin No. Mnemonic Description 47 I Current Output Pin for DAC Channel C. OUT_C 48 COMP DC-DC Compensation Capacitor. Connect capacitor from this pin to ground. Used to regulate the DCDC_C feedback loop of channel C’s DC-DC converter Buffered Analog Output Voltage for DAC Channel C. OUT_C 50 +V Sense connection for the positive voltage output load connection for V ...
Page 15
... Figure 7. Iout settling 0-24mA though 1kΩ load, AV DCDC frequency=250kHz, C varied. (See Figure 21) DCDC Figure 8. Iout settling 0-24mA though 1kΩ load, AV DCDC frequency=406kHz, C varied. (See Figure 21) DCDC TBD Figure 9 =3.0V, L =10uH, cc DCDC =3.0V, L =10uH, cc DCDC Rev. PrD| Page AD5755-1 TBD Figure 10. TBD Figure 11. TBD Figure 12 ...
Page 16
... AD5755-1 THEORY OF OPERATION The AD5755 quad, precision digital to current loop and voltage output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost single-chip solution for generating current loop and unipolar/bipolar voltage outputs. The current ranges available are 20mA 24mA and 4 to 20mA, the voltage ranges available are ...
Page 17
... SDIN Figure 16. Simplified Serial Interface of Input Loading Circuitryfor One DAC TRANSFER FUNCTION Table 10 shows the input code to ideal output voltage relationship for the AD5755-1 or straight binary data coding - ±10v output range shown. Table 7. Ideal Output Voltage to Input Code Relationship Digital Input ...
Page 18
... DATA REGISTERS Description DAC Data Register (X4) Used to write a DAC code to each DAC channel. AD5755-1 Data bits (D15 to D0), There are four DAC Data Registers, one per DAC Channel. Gain Register (X4) Used to program gain trim on per channel basis. AD5755-1 Data bits (D15 to D0), There are four Gain Registers, one per DAC channel ...
Page 19
... INT_Enable bit. Step 3: Write value to the DAC Data Register. Step 4: Write to DAC Control Register. Reload sequence as in Step 2 above.This time select the OUTEN bit to enable the output. Figure 18. Steps for Changing the Output Range Rev. PrD | Page AD5755-1 ...
Page 20
... It is possible to write the same gain code to all 4 DAC channels at the same time by setting the DREG bits to 011. The AD5755-1 Gain Register is a 16/12 bit register (bits G15.. G0/G3) and allows the user to adjust the gain of each channel in steps of 1 LSB as shown in the Table below. The Gain Register coding is straight binary. In theory the gain can be tuned across the full range of the output ...
Page 21
... DAC channel the offset write is addressed to possible to write the same offset code to all 4 DAC channels at the same time by setting the DREG bits to 101. The AD5755-1 offset code is 16/12 bit (bits OF15.. OF0/OF3) and allows the user to adjust the offset of each channel by −32768/8192 LSBs to +32767/8191 LSBs in steps of 1 LSB as shown in the Table below.. The Offset Register coding is straight binary ...
Page 22
... AD5755-1 CONTROL REGISTERS When writing to a data register the following format must be used: Table 17. Writing to a control register MSB D23 D22 D21 D20 D19 D18 D17 R/ W DUT_AD1 DUT_AD0 1 1 See for configuration on bits D23 to D16. The control registers are addressed by setting the DREG bits to DREG2 = 1, DREG1 = ...
Page 23
... Voltage Range 1 0 ±5V Voltage Range 1 1 ±10V Voltage Range Current Range Current Range Current Range LSB D11 to D0 RESET CODE/SPI CODE Rev. PrD | Page AD5755 RSET DC-DC OVRNG ...
Page 24
... AD5755-1 Table 24. Software Register Functions User Program Bit This bit is mapped to bit D11 of the Status Register. When this bit is set to 1 bit D11 of the Status Register is set to 1. Likewise when D12 is set to 0 bit D11 of the Status Register is also set to zero. This feature can be used to ensure the SPI pins are working correctly by writing known bit to this register and reading back corresponding bit from the Status Register ...
Page 25
... To read back the Gain Register of Device #1 Channel A on the AD5755-1, the following sequence should be implemented: 1. Write 0xA80000 to the AD5755-1 input register. This configures the AD5755-1 device address #1 for read mode with the Gain Register of channel A selected.. Note that all the data bits, D15 to D0, are don’t care. ...
Page 26
... This bit will be set while any one of the output channels are slewing (slew rate control enabled on at least one channel) OVER TEMP This bit will be set if the AD5755-1 core temperature exceeds approx. 150°C. PEC ERROR Denotes a PEC Error on the SPI Interface Transmit. ...
Page 27
... Preliminary Technical Data FEATURES OUTPUT FAULT The AD5755-1 is equipped with a FAULT pin, this is an active low open-drain output allowing several AD5755-1 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the following fault scenarios; ...
Page 28
... The watchdog timer is enabled and the timeout period (50,100,150 or 200ms) set in the control register (See Table 19). OUTPUT ALERT The AD5755-1 is equipped with a ALERT pin, this is An active high CMOS output. The AD5755-1 has an internal watchdog timer. If enabled, it will monitor SPI communications. If 0x195 is not received by the Software Register within the timeout period, the ALERT pin will go active ...
Page 29
... Digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for HART. SLEW RATE CONTROL The Slew Rate Control feature of the AD5755-1 allows the user to control the rate at which the output value changes. This feature is available on both the current and voltage outputs. ...
Page 30
... DC-DC Operation The on-board DC-DC converters use a constant frequency, peak current mode control scheme to step- the range 2.7 to 5.5v to drive the AD5755-1 output channel. These are designed to operate in discontinuous conduction mode (DCM) with a duty cycle < 85%. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable % of the switching cycle ...
Page 31
... Preliminary Technical Data Iout Slew Rate when using the DC-DC When the AD5755-1 is configured in Iout mode & a step increase in output current is programmed then the DCDC converter must increase its output voltage so that Vboost ≈ Iout*Rload+2v. This requires that the output capacitor of the DCDC circuit must also be charge to the new voltage ...
Page 32
... AD5755-1 is mounted should be designed so that the analog 3.4 and digital sections are separated and confined to certain areas of 3.4 the board. If the AD5755 system where multiple devices 15 require an AGND-to-DGND connection, the connection 5 should be made at one point only. The star ground point should be established as close as possible to the device ...
Page 33
... The power supply lines of the AD5755-1 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching ...
Page 34
... AD5755-1 OUTLINE DIMENSIONS 9.00 BSC SQ PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE Figure 24. 64-Lead Frame Chip Scale Package, 9x9 Quad. [LFCSP] ORDERING GUIDE Model Resolution AD5755-1x 16bit 0.60 MAX 48 0.50 8.75 BSC BSC SQ 0.50 0.40 33 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.20 REF 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Dimensions shown in millimeters ...