PCM1604 BURR-BROWN [Burr-Brown Corporation], PCM1604 Datasheet - Page 14

• Manufacturer Part Number: PCM1604
• Description: 24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

FIGURE 7. Write Operation Timing.
REGISTER WRITE OPERATION
All Write operations for the serial control port use 16-bit data
words. Figure 6 shows the control data word format. The most
significant bit is the Read/Write (R/W) bit. When set to ‘0’, this
bit indicates a Write operation. There are seven bits, labeled
IDX[6:0], that set the register index (or address) for the Write
operation. The least significant eight bits, D[7:0], contain the
data to be written to the register specified by IDX[6:0].
Figure 7 shows the functional timing diagram for writing the
serial control port. ML is held at a logic ‘1’ state until a register
needs to be written. To start the register write cycle, ML is set
to logic ‘0’. Sixteen clocks are then provided on MC, corre-
sponding to the 16-bits of the control data word on MDI. After
the sixteenth clock cycle has completed, ML is set to logic ‘1’
to latch the data into the indexed mode control register.
FIGURE 6. Control Data Word Format for MDI.
FIGURE 5. Audio Interface Timing.
DATA1-DATA3
®
MDI
MC
ML
LRCK
BCK
PCM1604, PCM1605
NOTE: (1) f
SYMBOL
t
t
t
t
t
t
t
BCY
BCH
BCL
BL
LB
DS
DH
X
MSB
R/W
0
S
IDX6
Read/Write Operation
0 = Write Operation
1 = Read Operation (register index is ignored)
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
t
is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)
BCH
LRCK Falling Edge to BCK Rising Edge
IDX5
Register Index (or Address)
BCK Rising Edge to LRCK Edge
t
BCY
IDX4
BCK Pulse Cycle Time
BCK High Level Time
BCK Low Level Time
DIN Set Up Time
IDX3
DIN Hold Time
PARAMETER
t
BCL
IDX2
t
DS
IDX1 IDX0
t
DH
14
D7
t
BL
D7
SINGLE REGISTER READ OPERATION
Read operations utilize the 16-bit control word format shown
in Figure 6. For Read operations, the Read/Write (R/W) bit is
set to ‘1’. Read operations ignore the index bits, IDX[6:0], of
the control data word. Instead, the REG[6:0] bits in Control
Register 11 are used to set the index of the register that is to be
read during the Read operation. Bits IDX[6:0] should be set to
00
Figure 8 details the Read operation. First, Control Register 11
must be written with the index of the register to be read back.
Additionally, the INC bit must be set to logic ‘0’ in order to
disable the Auto-Increment Read function. The Read cycle is
then initiated by setting ML to logic ‘0’ and setting the R/W bit
of the control data word to logic ‘1’, indicating a Read
operation. MDO remains at a high-impedance state until the
D6
H
D6
for Read operations.
D5
MIN
D5
35
35
10
10
10
10
D4
Register Data
t
D4
LB
D3
48 or 64f
D3
D2
MAX
D2
D1
S
(1)
D1
D0
UNITS
LSB
D0
X
ns
ns
ns
ns
ns
ns
X
D15 D14
50% of V
50% of V
50% of V
DD
DD
DD