ADS8472I BURR-BROWN [Burr-Brown Corporation], ADS8472I Datasheet - Page 6

• Manufacturer Part Number: ADS8472I
• Description: 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

ADS8472
SLAS514 – DECEMBER 2006
6
TIMING CHARACTERISTICS
All specifications typical at –40 C to 85 C, +VA =+VBD = 5 V
(1) All input signals are specified with t
(2) See timing diagrams.
(3) All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
(CONV)
(ACQ)
(HOLD)
pd1
pd2
pd3
w1
su1
w2
w3
w4
h1
d1
su2
w5
en
d2
d3
w6
w7
h2
pd4
d4
su3
h3
dis
d5
d6
d7
su5
su(ABORT)
Conversion time
Acquisition time
Sample capacitor hold time
CONVST low to BUSY high
Propagation delay time, end of conversion to BUSY low
Propagation delay time, start of convert state to rising edge of BUSY
Pulse duration, CONVST low
Setup time, CS low to CONVST low
Pulse duration, CONVST high
CONVST falling edge jitter
Pulse duration, BUSY signal low
Pulse duration, BUSY signal high
Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE input
changes) after CONVST low
Delay time, CS low to RD low
Setup time, RD high to CS high
Pulse duration, RD low
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
Delay time, BYTE rising edge or falling edge to data valid
Pulse duration, RD high
Pulse duration, CS high
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
edge
Delay time, BYTE edge to edge skew
Setup time, BYTE transition to RD falling edge
Hold time, BYTE transition to RD falling edge
Disable time, RD high (CS high for read cycle) to 3-stated data bus
Delay time, BUSY low to MSB data valid delay
Delay time, CS rising edge to BUSY falling edge
Delay time, BUSY falling edge to CS rising edge
BYTE transition setup time, from BYTE transition to next BYTE transition.
Setup time from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the
next falling edge of CS (when CS is used to abort).
r
= t
PARAMETER
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
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(1) (2) (3)
t
(ACQ)
MIN
320
min
40
20
20
40
50
10
20
20
50
10
10
50
50
50
60
0
0
5
0
0
IL
+ V
TYP
625
350
IH
)/2.
MAX
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650
650
550
25
40
15
15
10
20
20
20
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns