AD9022AQ AD [Analog Devices], AD9022AQ Datasheet - Page 7

• Manufacturer Part Number: AD9022AQ
• Description: 12-Bit 20 MSPS Monolithic A/D Converter
• Manufacturer: AD [Analog Devices]

THEORY OF OPERATION
Refer to the block diagram.
The AD9022 employs a three-pass subranging architecture and
digital error correction. This combination of design techniques
ensures 12-bit accuracy at relatively low power.
Analog input signals are immediately attenuated through a
resistor divider and applied directly to the sampling bridge of
the track-and-hold (T/H). The T/H holds whatever analog value
REV. B
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
100
120
60
80
20
40
0
0
0
0.0
0
0
A
A
SNR = 66.05dB
THD = 74.28dB
SFDR = 75.32dBFS
A
A
A
A
SFDR = 80.62dBFS
IN
IN
IN1
IN2
IN1
IN2
= 9.6MHz
= –1.0dBFS
= 9.8MHz
= 7.0dBFS
= 8.9MHz
= 7.0dBFS
Figure 10. Two-Tone FFT
2.0
Figure 8. FFT Plot
Figure 9. FFT Plot
FREQUENCY – MHz
FREQUENCY – MHz
FREQUENCY – MHz
4.0
6.0
A
A
SNR = 66.7dB
THD = 77.51dB
SFDR = 79.49dBFS
IN
IN
= 1.2MHz
= –1.0dBFS
8.0
10.0
10
10
–7–
is present when the unit is strobed with an ENCODE com-
mand. The conversion process begins on the rising edge of this
pulse, which should conform to the minimum and maximum
pulsewidth requirements shown in the specifications. Operation
below the recommended encode rate (4 MSPS) may result in
excessive droop in the internal T/H devices–leading to large dc
and ac errors.
The held analog value of the first track-and-hold is applied to a
5-bit flash converter and a second T/H. The 5-bit flash con-
verter resolves the most significant bits (MSBs) of the held
analog voltage. These five bits are reconstructed via a 5-bit
DAC and subtracted from the original T/H output signal to
form a residue signal.
A second T/H holds the amplified residue signal while it is en-
coded with a second 5-bit flash ADC. Again the five bits are
reconstructed and subtracted from the second T/H output to
form a residue signal. This residue is amplified and encoded
with a 4-bit flash ADC to provide the three least significant bits
(LSBs) of the digital output and one bit of error correction.
Digital Error Correction logic aligns the data from the three
flash converters and presents the result as a 12-bit parallel digi-
tal word. The output stage of the AD9022 is TTL. Output data
may be strobed on the rising edge of the ENCODE command.
AD9022 IN RECEIVER APPLICATIONS
Advances in semiconductor processes have resulted in low cost
digital signal processing (DSP) and analog signal processing
which can help create cost effective alternative receiver designs.
Today, an all-digital receiver allows tuning, demodulation, and
detection of receiver signals in the digital domain. By digitizing
IF signals directly, and utilizing digital techniques, it becomes
possible to make significant improvements in receiver design.
For high frequency IFs, the ADC is the key to the receiver’s
performance. Unfortunately, the specifications frequently used
by receiver designers and analog-to-digital (ADC) manufactur-
ers are often very different. Noise Figure and Intercept Point are
common measures of noise and linearity in analog RF system
design. ADCs are more frequently specified in terms of SNR
and harmonic distortion.
Noise
Noise figure (NF) is a measure of receiver sensitivity and is
defined as the degradation of signal-to-noise ratio (SNR) as a
signal passes through a device. In equation form:
Noise figure is a bandwidth invariant parameter for reasonably
narrow bandwidths in most devices. The system noise figure for
a combination of amplifiers and mixers, for instance, can be
analyzed without regard to the information bandwidth.
Thermal noise contribution from the ADC behaves in a similar
fashion; however, the spectral density of quantization noise is a
function of the sample rate. In addition, the spectral density of
the quantization noise is flat only in an ADC with perfect linear-
ity, i.e., perfect 1 LSB step sizes.
To analyze the system noise performance, ADC noise figure is
calculated by normalizing the SNR of the ADC output to a 1 Hz
bandwidth. This result is given by:
where F
S
is the sample rate.
SNR (/Hz) = SNR + 10 log
NF = SNR (in) – SNR (out)
10
(F
S
/2)
AD9022