AD9057-60 AD [Analog Devices], AD9057-60 Datasheet - Page 7

• Manufacturer Part Number: AD9057-60
• Description: 8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter
• Manufacturer: AD [Analog Devices]

THEORY OF OPERATION
The AD9057 combines Analog Devices’ proprietary MagAmp
gray code conversion circuitry with flash converter technology to
provide a high performance, low cost ADC. The design archi-
tecture ensures low power, high speed, and 8-bit accuracy. A
single-ended TTL/CMOS compatible ENCODE input controls
ADC timing for sampling the analog input pin and strobing the
digital outputs (D7–D0). An internal voltage reference (VREF
OUT) may be used to control ADC gain and offset or an exter-
nal reference may be applied.
The analog input signal is buffered at the input of the ADC and
applied to a high speed track-and-hold. The T/H circuit holds
the analog input value during the conversion process (beginning
with the rising edge of the ENCODE command). The T/H’s
output signal passes through the gray code and flash conversion
stages to generate coarse and fine digital representations of the
held analog input level. Decode logic combines the multistage
data and aligns the 8-bit word for strobed outputs on the rising
edge of the ENCODE command. The MagAmp/Flash architec-
ture of the AD9057 results in three pipeline delays for the out-
put data.
USING THE AD9057
Analog Inputs
The AD9057 provides a single-ended analog input impedance of
150 k . The input requires a dc bias current of 6 A (typical)
centered near +2.5 V ( 10%). The dc bias may be provided by
the user or may be derived from the ADC’s internal voltage
reference. Figure 14 shows a low cost dc bias implementation
allowing the user to capacitively couple ac signals directly into
the ADC without additional active circuitry. For best dynamic
performance, the VREF OUT pin should be decoupled to
ground with a 0.1 F capacitor (to minimize modulation of
the reference voltage) and the bias resistor should be approxi-
mately 1 k . A 1 k bias resistor ( 20%) is included within
the AD9057 and may be used to reduce application board size
and complexity.
Figure 15 shows typical connections for high performance dc
biasing using the ADC’s internal voltage reference. All compo-
nents may be powered from a single +5 V supply (in the example
analog input signals are referenced to ground).
REV. B
Figure 14. Capacitively Coupled AD9057
(1V p-p)
VIN
0.1µF
0.1µF
2
3
6
7
REF OUT
REF IN
BIAS OUT
AIN
1k
AD9057
+5V
–7–
Voltage Reference
A stable and accurate +2.5 V voltage reference is built into the
AD9057 (VREF OUT). The reference output may be used to
set the ADC gain/offset by connecting VREF OUT to VREF IN.
The internal reference is capable of providing 300 A of drive
current (for dc biasing the analog input or other user circuitry).
Some applications may require greater accuracy, improved
temperature performance, or gain adjustments which cannot be
obtained using the internal reference. An external voltage may
be applied to the VREF IN with VREF OUT disconnected for
gain adjustment of up to 10% (the VREF IN pin is internally
tied directly to the ADC circuitry). ADC gain and offset will
vary simultaneously with external reference adjustment with a
1:1 ratio (a 2% or 50 mV adjustment to the +2.5 V reference
varies ADC gain by 2% and ADC input range center offset by
50 mV). Theoretical input voltage range versus reference input
voltage may be calculated from the following equations:
Digital Logic (+5 V/+3 V Systems)
The digital inputs and outputs of the AD9057 can easily be
configured to interface directly with +3 V or +5 V logic systems.
The ENCODE and power-down (PWRDN) inputs are CMOS
stages with TTL thresholds of 1.5 V, making the inputs compat-
ible with TTL, +5 V CMOS, and +3 V CMOS logic families.
As with all high speed data converters, the encode signal should
be clean and jitter free to prevent degradation of ADC dynamic
performance.
The AD9057’s digital outputs will also interface directly with
+5 V or +3 V CMOS logic systems. The voltage supply pin
(V
voltage supply. By varying the voltage on this supply pin the
digital output HIGH level will change for +5 V or +3 V systems.
Optimum SNR is obtained running the outputs at +3 V. Care
should be taken to isolate the V
analog supply to minimize digital noise coupling into the ADC.
(–0.5V TO +0.5V)
DD
V
V
V
V
) for these CMOS stages is isolated from the analog V
VIN
RANGE
MIDSCALE
TOP-OF-RANGE
BOTTOM-OF-RANGE
Figure 15. DC Coupled AD9057 (Inverted VIN)
(p-p)
1k
+5V
= VREF IN/2.5
= VREF IN
= VREF IN + V
= VREF IN – V
1k
AD8041
10k
DD
10k
supply voltage from the +5 V
RANGE
0.1µF
RANGE
/2
/2
AD9057
2
3
7
REF OUT
REF IN
AIN
AD9057
+5V
D