HI3-5700A-9 INTERSIL [Intersil Corporation], HI3-5700A-9 Datasheet - Page 9

• Manufacturer Part Number: HI3-5700A-9
• Description: 8-Bit, 20 MSPS Flash A/D Converter
• Manufacturer: INTERSIL [Intersil Corporation]

Applications Information
Voltage Reference
The reference voltage is applied across the resistor ladder
between V
simply tied to analog ground such that the reference source
drives V
enough current to drive the minimum ladder resistance of
235Ω over temperature.
The HI-5700 is specified for a reference voltage of 4.0V, but
will operate with voltages as high as the V
case of 4.0V reference operation, the converter encodes the
analog input into a binary output in LSB increments of
(V
voltage reduces the LSB size proportionately and thus
increases linearity errors. The minimum practical reference
voltage is about 2.5V. Because the reference voltage
terminals are subjected to internal transient currents during
conversion, it is important to drive the reference pins from a
low impedance source and to decouple thoroughly. Again,
ceramic and tantalum (0.01µF and 10µF) capacitors near
the package pin are recommended. It is not necessary to
decouple the
applications.
It is possible to elevate V
this case, the V
impedance reference capable of sinking the current through
the
recommended.
CLOCK INPUT
REF
TO ANALOG +5V
TO ANALOG GND
+ - V
resistor
REF
REF
REF
+. The reference must be capable of supplying
10µF
1
+ and V
/
-)/256, or 15.6mV. Reducing the reference
4
ladder.
R,
50
REF
1
Ω
/
GROUND
2
DIGITAL
DIGITAL
- pin must be driven from a low
R, and
REF
V
DD
REF
Careful
-. In most applications, V
0.01µF
- from ground if necessary. In
OUTPUT
OUTPUT
3
/
4
PINS
PINS
R tap point pins for most
decoupling
DD
10
11
12
13
14
1
2
3
4
5
6
7
8
9
supply. In the
FIGURE 15. TEST CIRCUIT
CLK
D7
D6
D5
D4
1/4R
V
GND
3/4R
D3
D2
D1
D0
OVF
is
DD
REF
again
HI-5700
- is
4-1499
100
AGND
AGND
AGND
AGND
V
Ω
V
AV
AV
AV
AV
REF
Digital Control and Interface
The HI-5700 provides a standard high speed interface to
external CMOS and TTL logic families. Two chip enable
inputs control the three-state outputs of output bits D0
through D7 and the Overflow (OVF) bit. As indicated in the
Truth Table, all output bits are high impedance when CE2 is
low, and output bits D0 through D7 are independently
controlled by CE1.
Although the Digital Outputs are capable of handling typical
data bus loading, the bus capacitance charge/discharge
currents will produce supply and local group disturbances.
Therefore, an external bus driver is recommended.
Clock
The clock should be properly terminated to digital ground
near the clock input pin. Clock frequency defines the
conversion frequency and controls the converter as
described in the “Theory of Operation” section. The Auto
Balance φ1 half cycle of the clock may be reduced to
approximately 20ns; the Sample φ2 half cycle may be varied
from a minimum of 25ns to a maximum of 5µs.
Signal Source
A current pulse is present at the analog input (V
beginning of every sample and auto balance period. The
transient current is due to comparator charging and switch
feedthrough in the capacitor array. It varies with the
amplitude of the analog input and the converter’s sampling
REF
CE1
CE2
1
V
/
2
DD
DD
DD
DD
IN
R
+
-
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+5V
+9V TO +12V
+9V TO +12V
HA-5033
GROUND
ANALOG
0.01µF
0.01µF
0.01µF
0.01µF
0.01µF
10µF
10µF
10µF
10µF
10µF
REFERENCE
ANALOG
SIGNAL
INPUT
ANALOG
PRECISION
V
DD
IN
DC
) at the
(+5V)