TC3403 MICROCHIP [Microchip Technology], TC3403 Datasheet - Page 6

• Manufacturer Part Number: TC3403
• Description: +1.8V Low Power, Quad Input, 16-Bit Sigma-Delta A/D Converter with a Power Fault Monitor and Microprocessor Reset Circuit
• Manufacturer: MICROCHIP [Microchip Technology]

TC3403
3.0
The TC3403 has a 16-bit sigma-delta A/D converter. It
has two differential inputs, an analog multiplexer, a V
monitor with reset generator and an early warning
Power Fail detector. See the Typical Application circuit
and
components of the TC3403 are described below.
Also refer to Figure 3-5, A/D Operational Flowchart and
the Timing Diagrams, Figure 3-1, Figure 3-2 and
Figure 3-3.
3.1
When the TC3403 is not converting, it is in Sleep mode
with both the SCLK and SDAT lines high. An A/D con-
version is initiated by a high to low transition on the
SCLK line at which time the internal clock of the
TC3403 is started and the address value (A0 and A1)
is internally latched. The address value steers the ana-
log multiplexer to select the input channel to be con-
verted. Each additional high to low transition of SCLK
(following the initial SCLK falling edge) during the time
interval t
one bit and reduce the conversion time by one half. The
time interval t
window. The minimum conversion resolution is 10-bits
so any more than 6 SCLK transitions during t
ignored.
After each high to low transition of SCLK, in the t
interval, the SDAT output is driven high by the TC3403
to acknowledge that the resolution has been decre-
mented. When the SCLK returns high or the t
ends, the SDAT line returns low (see Figure 3-2). When
the conversion is complete SDAT is driven high. The
TC3403 now enters Sleep mode and the conversion
value can be read as a serial data word on the SDAT
line.
3.2
After the conversion is complete and SDAT goes high,
the conversion value can be clocked serially onto the
SDAT line by high to low transitions of the SCLK. The
data word is in two’s compliment format with the sign bit
clocked onto the SDAT line, first followed by the MSB
and ending in the LSB. For a 16-bit conversion the data
word would consist of a sign bit followed by 15 magni-
tude bits, Table 3-1 shows the data word versus input
voltage for a 16-bit conversion. Note that the full scale
input voltage range is ±(2 REF
REF
for a 16-bit conversion, as REF
Figure 3-4 shows typical SCLK and SDAT waveforms
for 16, 12 and 10-bit conversions. Note that any com-
plete convert and read cycle requires 17 negative edge
clock pulses. The first is the convert command. Then,
up to six of these can occur in the resolution reduction
window, t
pulses clock out the conversion data word.
DS21412B-page 6
OUT
the
4,
DETAILED DESCRIPTION
A/D Converter Operation
Reading the Data Word
is fed back directly to REF
4
will decrement the conversion resolution by
, to decrement resolution. The remaining
Functional
4
is referred to as the resolution reduction
Block
OUT
diagram.
IN
IN
is typically 1.193V.
, an LSB is 73µV
– 1LSB). When
The
4
4
interval
will be
key
DD
4
TABLE 3-1:
The SCLK input has a filter which rejects any positive
or negative pulse of width less than 50nsec to reduce
noise. The rejection width of this pulse can vary
between 50nsec and 750nsec depending on process-
ing parameters and supply voltage.
Figure 3-1 and Table 3-2 show information for deter-
mining the mode of operation for the TC3403 by
recording the value of SDAT for SCLK in a high, then
low, then high state. For example, if SCLK goes
through a 1-0-1 transition and the corresponding
values of SDAT are 1-1-0, then the SCLK falling edge
started a new data conversion. A 0-1-0 for SDAT would
have indicated a resolution reduction had occurred.
This is useful if the microcontroller has a Watchdog
Reset or otherwise loses track of where the TC3403 is
in the conversion and data readout sequence. The
microcontroller can simply transition SCLK until it
“finds” a Start Conversion condition.
FIGURE 3-1:
TABLE 3-2:
*
Note: The code X00 has a dual meaning: Data Transfer or
0111 1111 1111 1111
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
SDAT
SCLK
A
1
0
x
x
Busy converting. To avoid confusion, the user should
send only the required number of pulses for the
desired resolution, then wait for SDAT to rise to 1,
indicating conversion is complete before clocking
SCLK again to read out data bits.
Data Word
B
1
1
1
0
A
C
0
0
1
0
DATA CONVERSION WORD
VS. VOLTAGE INPUT
(REF
SCLK, SDAT LOGIC STATE
Start Conversion
Resolution Reduction
Data Transfer
Data Transfer or Busy*
STATE DIAGRAM
SCLK, SDAT LOGIC
©
IN
2002 Microchip Technology Inc.
= 1.193V)
2.38596 (Positive Full Scale)
72.8 E -6
0
-72.8 E -6
-2.38596 (Negative Full Scale)
Reserved Code
B
INn+ – INn- (Volts)
Status
C