AD5532-3 AD [Analog Devices], AD5532-3 Datasheet - Page 12

• Manufacturer Part Number: AD5532-3
• Description: 32-Channel, 14-Bit Voltage-Output DAC
• Manufacturer: AD [Analog Devices]

AD5532
This is useful in an application where the user wants to ramp up
V
not need to be acquired continuously while it is ramping up.
TRACK can be kept low and only when V
desired voltage is TRACK brought high. At this stage, the
acquisition of V
In the example shown, a desired voltage is required on the out-
put of the pin driver. This voltage is represented by one input to
a comparator. The microcontroller/microprocessor ramps up
the input voltage on V
while the voltage on V
ally acquired. When the desired voltage is reached on the output
of the pin driver, the comparator output switches. The µC/µP
then knows what code is required to be input in order to obtain
the desired voltage at the DUT. The TRACK input is now
brought high and the part begins to acquire V
BUSY goes low until V
is then switched from V
MODES OF OPERATION
The AD5532 can be used in four different modes of opera-
tion. These modes are set by two mode bits, the first two bits in
the serial word.
Mode Bit 1
0
0
1
1
1. DAC Mode
In this standard mode a selected DAC register is loaded serially.
This requires a 24-bit write (10 bits to address the relevant DAC
plus an extra 14 bits of DAC data). MSB is written first. The
user must allow 400 ns (min) between successive writes in DAC
mode.
2. SHA Mode
In this mode a channel is addressed and that channel acquires
the voltage on V
ure 21) to address the relevant channel (V
channel or all channels) MSB is written first.
3. Acquire and Readback Mode
This mode allows the user to acquire V
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and V
Following the acquisition, after the next falling edge of SYNC,
the data in the relevant DAC register is clocked out onto the
IN
until V
OUT
CONTROLLER
reaches a particular level (Figure 18). V
IN
IN
Table II. Modes of Operation
. This mode requires a 10-bit write (see Fig-
begins.
Mode Bit 2
0
1
0
1
IN
IN
IN
IN
through a DAC. TRACK is kept low
ramps up so that V
has been acquired. The output buffer
to the output of the DAC.
DAC
IN
TRACK
is acquired in 16 µs (max).
BUSY
V
IN
IN
Operating Mode
SHA Mode
DAC Mode
Acquire and Readback
Readback
and read back the data
ONLY ONE CHANNEL SHOWN FOR SIMPLICITY
OUT
OUT
IN
0–V
has reached its
IN
is not continu-
ACQUISITION
. At this stage
OUT
CIRCUIT
31, offset
IN
does
D
must elapse before the DAC register data can be clocked out.
4. Readback Mode
Again, this is a readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of SYNC, the data in the relevant DAC
register is clocked out onto the D
The user must allow 400 ns (min) between the last SCLK fall-
ing edge in the 10-bit write and the falling edge of SYNC in
the 14-bit readback. The serial write and read words can be
seen in Figure 19.
This feature allows the user to read back the DAC register code
of any of the channels. In DAC mode this is useful in verification
of write cycles. In SHA mode readback is useful if the system
has been calibrated and the user wants to know what code in
the DAC corresponds to a desired voltage on V
requires this voltage again, he can input the code directly to the
DAC register without going through the acquisition sequence.
INTERFACES
Serial Interface
The SER/PAR pin is tied high to enable the serial interface and
to disable the parallel interface. The serial interface is controlled
by four pins as follows:
Mode Bits
There are four different modes of operation as described above.
Cal Bit
In DAC mode this is a test bit. When it is high it is used to load
all zeros or all ones to the 32 DACs simultaneously. In SHA mode
all 32 channels acquire V
In SHA mode the acquisition time is then 45 µs (typ) and accu-
racy may be reduced. This bit is set low for normal operation.
Offset_Sel Bit
If this is set high, the offset channel is selected and Bits A4–
A0 are ignored.
Test Bit
This must be set low for correct operation of the part.
A4–A0
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
OUT
D
Data Out pin for reading back the contents of the DAC
registers. The data is clocked out on the rising edge of SCLK
and is valid on the falling edge of SCLK.
SYNC, D
Standard 3-wire interface pins. The SYNC pin is shared
with the CS function of the parallel interface.
AD5532
OUTPUT
STAGE
OUT
line in a 14-bit serial format. The full acquisition time
TRACK
IN
, SCLK
V
OUT
1
DRIVER
THRESHOLD
PIN
VOLTAGE
IN
simultaneously when this bit is high.
OUT
line in a 14-bit serial format.
DEVICE
UNDER
TEST
OUT
. If the user