UDA1342 PHILIPS [NXP Semiconductors], UDA1342 Datasheet - Page 33

• Manufacturer Part Number: UDA1342
• Description: Audio CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Notes
1. The typical value of the timing is specified at 48 kHz sampling frequency.
2. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as
3. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to
4. C
5. After this period, the first clock pulse is generated.
6. To be suppressed by the input filter.
2000 Mar 29
t
t
t
t
t
t
t
I
f
t
t
t
t
t
t
t
t
t
t
t
C
stp(L3)
su(L3)DA
h(L3)DA
su(L3)R
h(L3)R
en(L3)R
dis(L3)R
2
SCL
LOW
HIGH
r
f
HD;STA
SU;STA
SU;STO
BUF
SU;DAT
HD;DAT
SP
C-bus interface timing (see Fig.15)
b
Audio CODEC
SYMBOL
small as possible.
b
is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
L3MODE stop time in data
transfer mode
L3DATA set-up time in address
and data transfer mode
L3DATA hold time in address and
data transfer mode
L3DATA set-up time for read data
L3DATA hold time for read data
L3DATA enable time for read data
L3DATA disable time for read data
SCL clock frequency
SCL LOW time
SCL HIGH time
rise time SDA and SCL
fall time SDA and SCL
hold time START condition
set-up time repeated START
set-up time STOP condition
bus free time between a STOP
and START condition
data set-up time
data hold time
pulse width of spikes
capacitive load for each bus line
PARAMETER
note 4
note 4
note 5
note 6
CONDITIONS
33
190
190
30
50
360
380
50
0
1.3
0.6
20 + 0.1C
20 + 0.1C
0.6
0.6
0.6
1.3
100
0
0
MIN.
b
b
TYP.
1
64fs
Preliminary specification
cycle.
UDA1342TS
400
300
300
50
400
MAX.
ns
ns
ns
ns
ns
ns
ns
kHz
ns
ns
ns
ns
pF
s
s
s
s
s
s
s
UNIT